Dec 1, 2015 - 5 ways FPGA-based prototyping shrinks design time,
Jan 27, 2015 - Did we say "a few"? Who's counting? We just know the topic range here spans everything from what designers ready to work on PCIe 4.0 projects should know to SoCs and design ...
Register structure and memory modeling is a very complex task of any verification methodology. - Paul Lungu, Bo Zhu, Synopsys - April, 2008
Nov 18, 2015 - In this webinar, we will discuss how to take advantage of the system-level capabilities of Synopsys Verification IP for ARM® AMBA® protocols to verify cache-coherent interconnects. ...
Design problems that appear in the late phases of the development cycle can be extremely difficult to track down and debug, thus putting project schedules at risk. This whitepaper presents the ...
This blog is dedicated to system-level design and embedded software - Achim Nohl
May 18, 2017 - Acacia Communications has successfully deployed Synopsys VCS Fine-Grained Parallelism (FGP) technology in production, to reduce regression turnaround time (TAT) by 2X.
This whitepaper introduces driver development for DesignWare IP in the context of ARM-based systems using Synopsys Virtualizer Development Kits (VDKs). - November, 2015
Jun 21, 2016 - This 60-minute Webinar will provide an overview of virtual hardware ECUs and how to integrate them into the automotive system development process to manage these challenges.
Nov 8, 2016 - Discover how native integrations of Verdi design debug technologies with Synopsys’ power analysis and verification solutions help catch power-related bugs earlier and faster.