5 ways FPGA-based prototyping shrinks design time
Dec 1, 2015 - 5 ways FPGA-based prototyping shrinks design time,
A Few Questions on… FPGA-based Prototyping Software Tools
Jan 27, 2015 - Did we say "a few"? Who's counting? We just know the topic range here spans everything from what designers ready to work on PCIe 4.0 projects should know to SoCs and design ...
A Fully Reusable Register Memory Access Solution Using VMM RAL
Register structure and memory modeling is a very complex task of any verification methodology. - Paul Lungu, Bo Zhu, Synopsys - April, 2008
A Holistic Approach to Verification: Synopsys VIP for ARM AMBA Cache Coherent...
Nov 18, 2015 - In this webinar, we will discuss how to take advantage of the system-level capabilities of Synopsys Verification IP for ARM® AMBA® protocols to verify cache-coherent interconnects. ...
A Simple Way to Debug IIP-Based Designs and SoCs: Using the Verdi Transaction...
Design problems that appear in the late phases of the development cycle can be extremely difficult to track down and debug, thus putting project schedules at risk. This whitepaper presents the ...
A View from the Top: A System-Level Blog
This blog is dedicated to system-level design and embedded software - Achim Nohl
Acacia Communications Reduces Simulation Regression Turnaround Time by 2X ...
May 18, 2017 - Acacia Communications has successfully deployed Synopsys VCS Fine-Grained Parallelism (FGP) technology in production, to reduce regression turnaround time (TAT) by 2X.
Accelerate DesignWare IP Driver Development for ARM-Based Designs
This whitepaper introduces driver development for DesignWare IP in the context of ARM-based systems using Synopsys Virtualizer Development Kits (VDKs). - November, 2015
Accelerate Development of Powertrain ECUs with Virtual Hardware
Jun 21, 2016 - This 60-minute Webinar will provide an overview of virtual hardware ECUs and how to integrate them into the automotive system development process to manage these challenges.