Verification Resources

Sort by

Synopsys Suggests

10 Must Knows About Virtual Prototypes

Feb 27, 2014 - What is a virtual prototype? Not all virtual prototypes are the same, not everyone defines them the same way, and not all of them work together. But they still can be very useful.

2014 HSPICE SIG Event: Signal Integrity with Best-in-Class Transistor-level ...

On January 28, 2014, Synopsys hosted an HSPICE SIG Event in Santa Clara, CA. At this event, industry leaders spoke about their experiences using HSPICE for signal and power integrity analysis of ...

5 ways FPGA-based prototyping shrinks design time

Dec 1, 2015 - 5 ways FPGA-based prototyping shrinks design time,

A Few Questions on… FPGA-based Prototyping Software Tools

Jan 27, 2015 - Did we say "a few"? Who's counting? We just know the topic range here spans everything from what designers ready to work on PCIe 4.0 projects should know to SoCs and design ...

A Fully Reusable Register Memory Access Solution Using VMM RAL

Register structure and memory modeling is a very complex task of any verification methodology. - Paul Lungu, Bo Zhu, Synopsys - April, 2008

A Holistic Approach to Verification: Synopsys VIP for ARM AMBA Cache Coherent...

Nov 18, 2015 - In this webinar, we will discuss how to take advantage of the system-level capabilities of Synopsys Verification IP for ARM® AMBA® protocols to verify cache-coherent interconnects. ...

A Safe Approach to Hierarchical UPF Verification in Formality

The IEEE-1801 IEEE Standard for Design and Verification of LowPower Integrated Circuits (UPF) adds additional constraints on the design affecting synthesis and verification. Using Formality with ...

A Simple Way to Debug IIP-Based Designs and SoCs: Using the Verdi Transaction...

Design problems that appear in the late phases of the development cycle can be extremely difficult to track down and debug, thus putting project schedules at risk. This whitepaper presents the ...

A View from the Top: A System-Level Blog

This blog is dedicated to system-level design and embedded software - Achim Nohl

Acacia Communications Reduces Simulation Regression Turnaround Time by 2X ...

May 18, 2017 - Acacia Communications has successfully deployed Synopsys VCS Fine-Grained Parallelism (FGP) technology in production, to reduce regression turnaround time (TAT) by 2X.