This whitepaper explores DTL and how it can significantly improve TAT. - June 2020
Register structure and memory modeling is a very complex task of any verification methodology. - Paul Lungu, Bo Zhu, Synopsys - April, 2008
Jun 19, 2019 - The intention of this webinar is to address any concerns and convince the audience that if you're a Designer or a DV engineer, Formal Verification is your new best friend.
An increasing demand for reducing cost and time effort of the design process via improved CAE (Computer-Aided Engineer) tools and methods has characterized the automotive industry over the past two...
Apr 29, 2020 - In this webinar, we will discuss these new formal signoff metrics and how VC Formal enables users to achieve verification completeness.
This white paper describes the use of the industry-leading Synopsys Verification Continuum™ Platform solution and shows how it can be used to verify a real-world design. - December 2019
This blog is dedicated to system-level design and embedded software - Achim Nohl
May 18, 2017 - Acacia Communications has successfully deployed Synopsys VCS Fine-Grained Parallelism (FGP) technology in production, to reduce regression turnaround time (TAT) by 2X.
Jan 22, 2019 - This webinar introduces three techniques in Synopsys VC LP to tackle design verification for low power designs.
Feb 28, 2019 - Start development early on the complex firmware required by next generation SSDs.