Verification Resources

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Synopsys Suggests

DVCon US 2019

Feb 25, 2019 - See Synopsys at DVCon US 2019 to learn about the Verification Continuum combining best-in-class technology, including simulation, verification IP, emulation, advanced debug, static ...

AMS SIG India 2019

Feb 6, 2019 - At this live Analog Mixed-Signal (AMS) SIG event in India, distinguished speakers from leading companies will share their insights about using Synopsys' custom design and AMS ...

HSPICE SIG 2019

Jan 30, 2019 - This event is for all HSPICE and FineSim SPICE users and design engineers who want to stay connected with the latest developments in the field of circuit simulation. The evening ...

SpyGlass Early & Often – Lint & CDC for Every Block

Jan 24, 2019 - This SpyGlass webinar explores Lint and CDC as a design problem, not a signoff problem, where early and often is also required.

Efficient Hierarchical Verification For Low Power Designs

Jan 17, 2019 - This article discusses how tools using new hierarchical verification technologies, such as Synopsys Low Power Verification, enable a “shift-left” in the overall verification TAT and ...

Efficient Low Power Verification & Debug Methodology Using Power-Aware ...

Dec 13, 2018 - This article discusses using the capabilities of a power aware simulator coupled with an intuitive and powerful debug to ensure that subtle bugs do not escape silicon.

SiC MOSFET vs. Si IGBT in Electric Vehicle Applications

Dec 6, 2018 - This 20-minute Tech Talk compares SiC MOSFET and Si IGBT in electric vehicle applications. In addition, it analyzes a quantitative estimate of the system improvement based on ...

Efficient Low Power Verification and Debug Methodology Using Power Aware ...

Dec 5, 2018 - This webinar will share a methodology for efficient low power verification and debug enabling “shift-left” and ensuring that subtle bugs do not escape to silicon.

Formal Signoff

What’s good enough coverage? What makes one assertion better than another? Find out in this video as well as where the potential holes are in verification.

Verifying Clock Domain Crossings in UPF-based Low-power SoCs

Dec 3, 2018 - This article discusses the verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.