Verification Resources

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AI and Formal: A Winning Formula to Accelerate Verification Progress

Jan 27, 2021 - In this Synopsys Webinar, we will explore ML techniques being used in VC Formal Regression Mode Accelerator (RMA) App to accelerate verification progress, improving performance by ...

EuclidE: IDE with Design and Testbench On the Fly Checks

EuclidE is an integrated development environment intended for chip designers and verification engineers. It helps to cut project time, avoid re-spins, improve code quality, and reduce chip area and...

Portable Stimulus from IP to SoC CoStart Datasheet

As products become more complex and market windows shrink, we need to understand what improves efficiency in verification and how can these improvements be achieved?

Verification CoStart Verdi Datasheet

Debugging regression failures is a tedious process and can impact project schedules.

AWS Deploys Synopsys VCS on Arm-based AWS Graviton2 to Accelerate SoC ...

Dec. 17, 2020 – Synopsys, Inc. today announced that Amazon Web Services, Inc. (AWS) has deployed VCS® Fine-Grained Parallelism (FGP) technology running on Arm®-based Graviton2 servers.

Virtual Prototyping Next-Gen Automotive Microcontrollers

Dec 10, 2020 - This 30-minute Webinar presents the usage and benefits of virtual prototyping for a wide range of use cases for Infineon’s next-generation AURIXTM TC4xx automotive microcontrollers.

AImotive Deploys Synopsys VCS to Verify Next-Generation Automated Driving ...

Dec 9, 2020 - AImotive has adopted Synopsys VCS® simulation and Verdi® debug, part of the Verification Continuum® Platform, to help verify its innovative aiWare™ hardware IP for Neural Network (NN)...

From System to Software: A Study in Efficient, Robust Design for Electric ...

Dec 02, 2020 - This Tech Talk discusses how a unified virtual prototyping solution, which addresses the multi-discipline needs of system, electro-mechanical, and embedded software domains, can help...

Virtual Prototyping For Power Electronics Systems

Nov 24, 2020 - Learn more about how using piecewise linear circuit models rather than models with full SPICE-level accuracy to perform earlier simulation.

Silo Busting In The Design Flow

Nov 24, 2020 - Learn more about how Waterfall development flows no longer work for chip design, but unified tool flows may not be the answer.