Verification Resources

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Achieving Faster Closure using Advanced RTL Static Signoff Platform

Apr 29, 2021 - This Synopsys webinar delves into challenges of a typical static solution as a point tool and how VC SpyGlass RTL signoff solution can help address these challenges.

Synopsys Extends Market Leadership in Verification Hardware with Performance ...

Apr 05, 2021 - HAPS-100, the latest innovation in prototyping, delivers the fastest performance, highest debug productivity and unmatched enterprise scalability to accelerate software development, ...

Designing Secure and Trusted Silicon Using Shift-Left in Verification - GOMAC...

This technical paper from GOMAC 2021 provides insight into RDC verification technologies that can handle today's design and reset complexities.

Verdi - Unified Debug System: Tips for debugging and Introduction to Verdi ...

Mar 24, 2021 - This Synopsys Webinar provides tips for debugging and an introduction to Verdi Ultra, a unified debug system.

Semiconductor360 LIVE 2021 – Virtual Event

Mar 16, 2021 – Join us for semiconductor360 LIVE 2021, the first international virtual event by semiconductor360.com, for the international semiconductor community, as a flexible, quick, and ...

VC Formal SIG Europe 2021

March 16, 2021 - You’ll hear about groundbreaking applications and successful deployments of formal verification from industry leaders.

The Future is Virtual for Automotive Electronic System Software Development

Mar 09, 2021 - This Tech Talk provides an overview on how virtual prototyping accelerates a “Shift Left” and “Software First” perspective in automotive software development and test.

Making Sure AI/ML Works In Test Systems

Mar 09, 2021 - Artificial intelligence and machine learning is being utilized increasingly to find patterns and outlier data in chip manufacturing and test, improving the overall yield and ...

Synopsys Announces Euclide to Accelerate Design and Verification Productivity

Mar 03, 2021 - Synopsys introduces Euclide, the industry's next-generation hardware description language (HDL)-aware integrated development environment (IDE).

Using VCS, Verdi, and VIP to Reduce Verification Turnaround Time (Part 1)

Feb 24, 2021 - Part 1 of this Synopsys webinar series explores subsystem verification challenges and how to address them with innovations in Synopsys verification IP, specifically the new CXL ...