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A Simple Way to Debug IIP-Based Designs and SoCs: Using the Verdi Transaction...

Design problems that appear in the late phases of the development cycle can be extremely difficult to track down and debug, thus putting project schedules at risk. This whitepaper presents the ...

Accelerate DesignWare IP Driver Development for ARM-Based Designs

This whitepaper introduces driver development for DesignWare IP in the context of ARM-based systems using Synopsys Virtualizer Development Kits (VDKs). - November, 2015

Accelerating Analog Simulation with HSPICE Precision Parallel Technology

HSPICE Precision Parallel technology is a new multicore transient simulation extension to HSPICE for both pre- and post-layout of complex analog circuits such as PLLs, ADCs, DACs, SERDES, and other...

Address Simulation Turn-Around Time Bottlenecks with VCS Fine-Grained ...

This white paper describes VCS Fine-Grained Parallelism (FGP) technology and how it compares with alternate technologies. - February 2019

Addressing IP Integration & Software Development Challenges to Accelerate SoC...

This white paper will explore the issues facing SoC designers as they address SoC complexity and time-to-market challenges. It will discuss the use of third-party IP while noting that high-quality ...

Advanced Power and Performance Optimization for Multicore SoCs

The Multicore Optimization (MCO) technology in Synopsys Platform Architect provides an environment for early exploration and optimization of complex Multicore SoC (MP-SoC) platforms. It allows ...

Advanced Verification IP Accelerates PCIe Integration Test

PCI Express is an excellent example of where design reuse and adoption has become the norm for design teams, so while the verification teams are no longer faced with full compliance testing they ...

Analyzing the Losses in Visually Lossless Compression Algorithms

Learn about some interesting methods to analyze the quality of compression algorithms, in addition to observations about VESA Display Stream Compression using these algorithms. - October 2017

Automated Regression for Mixed-Signal Verification

CustomExplorer™ Ultra represents the next generation in mixed-signal verification environment, including regression management, debug and analysis for complex SoC design. - Duncan McDonald, Product...

Busting the 3 Big Common Myths About Physical Prototyping

This white paper discusses several common misperceptions about physical prototyping with FPGAs and their inherit limitations have largely been eliminated by the capacity, automation, and ...