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PLL Noise Analysis with HSPICE RF

This white paper describes a procedure for efficiently extracting key noise measurements for a phase locked loop using HSPICE RF. The procedure has been updated to take advantage of several new and...

FinFET Technology – Understanding and Productizing a New Transistor From TSMC...

This white paper discusses the major challenges with FinFETs and how TSMC has been collaborating with Synopsys, one of their ecosystem partners, to deliver a complete solution. Key elements of this...

Joint Optimization of Hardware and Compiler: Modeling AI Accelerators Using ...

This presentation proposes a novel approach for joint optimization of algorithms/compilers and hardware architecture. The top-down/integrated approach that leverages the latest machine learning ...

Is Your Automotive Software Robust Enough for Hardware Faults? Part 1: Fault ...

In this whitepaper we describe how virtual prototyping is expanding its reach to improve development of safety critical systems and deal with the single most complex aspect of automotive systems: ...

Is Your Automotive Software Robust Enough for Hardware Faults? Part 2: ...

In this whitepaper, we will apply virtual Fault Mode and Effect Analysis (FMEA) concepts on a specific case study, an Electrical Vehicle Powertrain (EVP) system. We will show how this EVP system is...

Continuous Integration and Automation With Virtualizer Development Kits

This whitepaper describes how simulation-based Virtualizer Development Kits are the perfect technology to remove the dependency with hardware and to enable the integration and testing of hardware ...

Methods and Tools for Bring-Up and Debug of an FPGA-Based ASIC Prototype

Software simulation of RTL is no longer capable of providing all of the verification required for today's complex ASIC designs. Modern ASICs are a complex mixture of hardware and software, so it is...

Using PCIe Real World Interface for High-Speed Hybrid Prototyping

This white paper highlights a novel approach to hybrid prototyping using a PCIe interface between the HAPS® FPGA-based prototyping and the Virtualizer® virtual prototyping. - November 2019

Optimizing DDR Memory Subsystem Efficiency - Part 1

Part 1 – The Unpredictable Memory Bottleneck The memory subsystem sits at the core of a System-on-Chip (SoC) platform and can make all the difference between a well-designed system meeting its ...

Optimizing DDR Memory Subsystem Efficiency - Part 2

Part 2 – A Mobile Application Processor Case Study This whitepaper applies virtual prototyping tools and best practice techniques to optimize the DDR memory subsystem configuration for a specific ...