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Analyzing the Losses in Visually Lossless Compression Algorithms

Learn about some interesting methods to analyze the quality of compression algorithms, in addition to observations about VESA Display Stream Compression using these algorithms. - October 2017

A Simple Way to Debug IIP-Based Designs and SoCs: Using the Verdi Transaction...

Design problems that appear in the late phases of the development cycle can be extremely difficult to track down and debug, thus putting project schedules at risk. This whitepaper presents the ...

VCS Fine-Grained Parallelism Simulation Performance Technology

Learn how fine-grained parallelism simulation technology enables delivery of breakthrough parallel simulation performance improvement needed to reduce turn-around time for critical-path tests. - ...

Synopsys SoundWire Test Suite

Validation and interoperability are always a challenge for any new protocol. In my earlier whitepaper, Digital Audio Simplified: MIPI SoundWire, I discussed the basics of digital audio ...

From Specification to Virtual Prototype: A Virtualizer Studio Case Study

Differentiation and success for any embedded system comes from how effectively and rapidly new software features can be added. System and semiconductor manufacturers that historically aimed only at...

Using VDKs for Automotive Systems Development

This white paper discusses the quantitative and qualitative analysis of the return on investment from VDKs. The software content of automotive systems found in powertrain, chassis, safety, body and...

Continuous Integration and Automation With Virtualizer Development Kits

This whitepaper describes how simulation-based Virtualizer Development Kits are the perfect technology to remove the dependency with hardware and to enable the integration and testing of hardware ...

Is Your Automotive Software Robust Enough for Hardware Faults? Part 2: ...

In this whitepaper, we will apply virtual Fault Mode and Effect Analysis (FMEA) concepts on a specific case study, an Electrical Vehicle Powertrain (EVP) system. We will show how this EVP system is...

Optimizing DDR Memory Subsystem Efficiency - Part 1

Part 1 – The Unpredictable Memory Bottleneck The memory subsystem sits at the core of a System-on-Chip (SoC) platform and can make all the difference between a well-designed system meeting its ...

Optimizing DDR Memory Subsystem Efficiency - Part 2

Part 2 – A Mobile Application Processor Case Study This whitepaper applies virtual prototyping tools and best practice techniques to optimize the DDR memory subsystem configuration for a specific ...