Verification Resources

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Achieving Faster Closure with Reduced Setup and Debug using Advanced RTL ...

Many design houses are continually seeking ways to shorten their effective design cycle to address demanding market requirements, gain a formidable technological advantage, and secure leadership in...

Shift Left Verification with Comprehensive Lint Signoff

This white paper focuses on advanced linting and how companies can implement shift left verification to catch design issues early using VC SpyGlass Lint capabilities. - June 2020

Eliminate Silicon Respins with Netlist CDC Verification

Clock domain crossing (CDC) verification has been an integral part of modern chip design flow for quite sometime. Traditionally CDC verification has been done during the RTL stage. However, for ...

Achieving CDC Signoff on Multi Billion Gate Designs with Hierarchical CDC Flow

For the last few decades, the System-on-Chip (SoC) design size has dramatically increased and more complexity has been introduced to deliver the desired functionality. A typical SoC can have many ...

Constraint-Based Verification of Clock Domain Crossings

This white paper provides background on clock domains and their verification challenges, and then presents a solution for thorough CDC verification. - March 2020

Exhaustive Verification of Reset Domain Crossings

This white paper provides some background on reset design challenges and discusses effective verification techniques using static technology. - March 2020

VC SpyGlass Lint: Early, Automated Detection of Design Issues

This white paper focuses on the categories of problems that can be found very early in the development process using linting technology, and specifically the capabilities of Synopsys VC SpyGlass ...

Four Steps for Static Verification of Low Power Designs Using UPF with VC LP

This white paper explains how to use the Synopsys VC LP static low power verification solution throughout this process at four stages: early UPF, UPF against RTL, UPF against post-synthesis ...