Jun 19, 2019 - The intention of this presentation is to address any concerns and convince the audience that if you're a Designer or a DV engineer, Formal Verification is your new best friend.
Apr 29, 2020 - See new formal signoff metrics and how VC Formal enables users to achieve verification completeness.
Jan 22, 2019 - This webinar introduces three techniques in Synopsys VC LP to tackle design verification for low power designs.
Aug 6, 2020 - Mike Dini, formerly of the Dini Group, will share his expertise in FPGA hardware and how FPGAs are being used to optimize low- and high-frequency trading (HFT) applications.
Oct 21, 2020 - In this Synopsys webinar, we will present how a virtual testing solution using Synopsys ZeBu and Keysight IxVerify tester software enables maximizing validation of realistic network ...
Apr 29, 2021 - This Synopsys webinar delves into challenges of a typical static solution as a point tool and how VC SpyGlass RTL signoff solution can help address these challenges.
Feb 27, 2019 - In this Synopsys webinar, we present how to use ZeBu to cut debug time after a failure has been reported during a multi-billion cycles regression.
Jul 24, 2019 - An introduction to the challenges of validation for complex networking SoCs with terabit per second throughput and high port counts. Learn why transitioning from traditional ...
Sep 2, 2020 - In this Synopsys webinar you will learn how Synopsys’ VC LP helps reduce the debug time drastically with smarter grouping and highlighting of root causes through intelligent analysis ...
Jun 17, 2020 - This is part three of our webinar series on how to achieve the best performance with VCS.