Verification Resources

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Why is Design Constraints (SDC) Validation Critical at RTL?

Mar 12, 2019 - In this webinar, we will talk about why constraint validation is important at RTL, highlight the different problems, and how designers can solve these problems early in the flow.

Increasing Debug Productivity with Verdi – Today’s Best Practices & Vision ...

Mar 7, 2019 - In this Synopsys webinar, we will show how Verdi helps design verification challenges, improves debug productivity, and give a preview of the future debug technology.

UPF Signoff Using Design Independent Checker

Mar 6, 2019 - This webinar will showcase the latest capabilities for UPF sign-off using the VC UPF methodology.

Addressing Exascale Emulation Debug Complexity – The case for a system-level ...

Feb 27, 2019 - In this webinar, we present how to use ZeBu to cut debug time after a failure has been reported during a multi-billion cycles regression.

An Efficient Hierarchical Verification Flow for Low Power Designs

Feb 21, 2019 - In this webinar, we will cover the benefits of SAM flow, such as the 8X-15X runtime performance gain and reduced memory consumption compared to the full flat verification, all while ...

SpyGlass Early & Often – Lint & CDC for Every Block

Jan 24, 2019 - This SpyGlass webinar explores Lint and CDC as a design problem, not a signoff problem, where early and often is also required.

SiC MOSFET vs. Si IGBT in Electric Vehicle Applications

Dec 6, 2018 - This 20-minute Tech Talk compares SiC MOSFET and Si IGBT in electric vehicle applications. In addition, it analyzes a quantitative estimate of the system improvement based on ...

Efficient Low Power Verification and Debug Methodology Using Power Aware ...

Dec 5, 2018 - This webinar will share a methodology for efficient low power verification and debug enabling “shift-left” and ensuring that subtle bugs do not escape to silicon.

Avoid Silicon Respins with Netlist CDC Verification (Part 2)

Nov 29, 2018 - This webinar will cover the Netlist CDC flow compatible with Static Timing Analysis (STA) and also show a brief demo on the tool capabilities. We will cover a few sample violations ...

Prevent Low Power Bugs Escaping to Silicon with VC LP for Debug

Nov 28, 2018 - This webinar shares techniques for efficient low power debug for simulation, synthesis and prototyping using Synopsys VC LP.