Verification Resources

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A Step-by-Step Approach to Formal Signoff

Apr 25, 2020 - In this webinar, we will discuss these new formal signoff metrics and how VC Formal enables users to achieve verification completeness.

Verifying Functional Safety Designs with Fault Simulation

Apr 14, 2020 - This webinar presents a methodology to effectively verify the functional safety logic implemented by Synplify Premier at the early stages of the design flow using fault ...

Debug Tips and Tricks to Improve VCS Simulation Performance (Part 2)

Apr 01, 2020 - This webinar will discuss how too much debug information can impact runtime performance and how faster, smarter debug can aid in improving productivity.

Why I Switched to Formal Verification – A SARC Case Study

Mar 25, 2020 - This webinar will explain a step-by-step approach on how to get started with formal verification to explore the design behavior.

Electric-Vehicle Transmission Development and Simulation

Mar 10, 2020 - Learn about the latest thinking in EV transmission engineering and the vital testing and simulation that accompany these efforts.

Getting the Most Out of VCS Simulation Performance (Part 1)

Feb 05, 2020 - This webinar explores Fine-Grained Parallelism (FGP) as one technology to improve performance by parallelizing the simulation across available cores.

Accelerate Low Power Static Verification with New Technologies in Synopsys VC...

Jan 22, 2019 - This webinar introduces three techniques in Synopsys VC LP to tackle design verification for low power designs.

Metastability Injection for CDC Signoff

Jan 21, 2020 - This webinar will explain a very robust solution that promises to address all these challenges, and also provides a very powerful debug mechanism using the best of both static and ...

Testbench Qualification for Simulation and Formal Verification Signoff

Jan 15, 2019 - This webinar will explore how functional qualification can be extended to assess and improve your verification environments and provide a new perspective on their completeness and ...

Synthesis of SystemVerilog RTL Constructs

Dec 20, 2019 - This webinar will help you understand the new synthesizable RTL constructs including the three new types of always blocks, priority, unique, wild equality, case inside, inside ...