Verification Resources

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The Future is Virtual for Automotive Electronic System Software Development

Mar 09, 2021 - This Tech Talk provides an overview on how virtual prototyping accelerates a “Shift Left” and “Software First” perspective in automotive software development and test.

Using VCS, Verdi, and VIP to Reduce Verification Turnaround Time (Part 1)

Feb 24, 2021 - Part 1 of this Synopsys webinar series explores subsystem verification challenges and how to address them with innovations in Synopsys verification IP, specifically the new CXL ...

Everything You Need to Know about SystemVerilog Arrays

Feb 10, 2021 - This Synopsys and Doulos webinar gives a comprehensive guide to all aspects of SystemVerilog arrays: ordinary static arrays, dynamic arrays, queues and associative arrays. It also ...

AI and Formal: A Winning Formula to Accelerate Verification Progress

Jan 27, 2021 - In this Synopsys Webinar, we will explore ML techniques being used in VC Formal Regression Mode Accelerator (RMA) App to accelerate verification progress, improving performance by ...

Virtual Prototyping Next-Gen Automotive Microcontrollers

Dec 10, 2020 - This 30-minute Synopsys and SAE Webinar presents the usage and benefits of virtual prototyping for a wide range of use cases for Infineon’s next-generation AURIXTM TC4xx automotive ...

From System to Software: A Study in Efficient, Robust Design for Electric ...

Dec 02, 2020 - This Tech Talk discusses how a unified virtual prototyping solution, which addresses the multi-discipline needs of system, electro-mechanical, and embedded software domains, can help...

How to Accelerate Power-Aware Simulation Debug with Synopsys’ VC LP

Nov 11, 2020 - This presentation demonstrates the benefits of running static checks prior to simulation, enabling simulation users to do quick static checks with Synopsys’ VC LP.

Low Power Verification – Challenges, Methodologies and Flows

Oct 29, 2020 - This Synopsys webinar will highlight how the low power verification challenges can be addressed proficiently by applying a combination of complimentary techniques covering static and...

Writing Structured Testbenches in VHDL

Oct 28, 2020 - This Synopsys and Doulos webinar introduces some modern verification concepts and shows how you can create a structured testbench in VHDL by presenting a VHDL testbench methodology.

Accelerating Validation of Next-Generation Cloud Architectures with Virtual ...

Oct 21, 2020 - In this Synopsys webinar, we will present how a virtual testing solution using Synopsys ZeBu and Keysight IxVerify tester software enables maximizing validation of realistic network ...