Verification Resources

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Synthesis of SystemVerilog RTL Constructs

Dec 20, 2019 - This webinar will help you understand the new synthesizable RTL constructs including the three new types of always blocks, priority, unique, wild equality, case inside, inside ...

Faster Verification Closure from IP to SoC Using the Verification Continuum ...

Dec 4, 2019 - The webinar delves into how the Synopsys end-to-end verification strategy scales from IP-level functional verification to full system-level validation & performance analysis using ...

Faster Software Development using Hybrid Prototyping over PCIe Real World ...

Nov 13, 2019 - What if you could perform early embedded software development and HW-SW co-validation at 125MHz FPGA-based prototyping speed with the debugging flexibility of virtual prototyping?

Getting Feedback in Minutes: Using a Virtual ECU to Accelerate Automotive ...

Nov 12, 2019 - Apart from sketching the technical foundation for virtual ECUs, this 30-minute Webinar covers recent applications from the powertrain, chassis, and ADAS/AV domain, all based on the ...

Finding Your Way Through Formal Verification

Oct 15, 2019 - This webinar serves as a foundation for how formal verification methods work, when and where to apply them and how it is managed in the overall verification objective.

Using Emulation to Close the SoC Power Analysis Gap

Sep 12, 2019 - In this webinar you will learn the basic methodology for software-driven power analysis and the advantages of ZeBu emulation technology to close the SoC power analysis gap.

Defining Timing Constraints using SDC

Sep 11, 2019 - This webinar will help you get started with building timing constraints for your digital design using the industry standard Synopsys Timing Constraints (SDC) format.

Constraints Driven CDC Methodology (Part 3)

Aug 28, 2019 - Part 3 of the webinar series will talk about machine learning-based Root Cause Analysis (RCA) for CDC. Machine learning RCA automatically identifies where to define constraints, ...

Harness Architectures: The Link Between Physical and Logical

Aug 21, 2019 - Synopsys SaberES Designer's Harness Architecture accelerates the total design process by using the same databases and automatically combining electrical system design information ...

AI-enabled Root Cause Analysis for Low Power Verification

Jul 30, 2019 - This webinar will talk about the current application of deterministic and machine learning-based techniques to automatically identify the accurate root-causes for a related group of ...