Verification Resources

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A Gentle Introduction to Formal Verification

Jun 19, 2019 - The intention of this webinar is to address any concerns and convince the audience that if you're a Designer or a DV engineer, Formal Verification is your new best friend.

Shift left Power Aware Static Verification using CDC and RDC

Jun 13, 2019 - This webinar discusses the verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.

Efficient Formal Verification with Smart Modeling

May 22, 2019 - In this webinar, we will provide insights on how we can build efficient and reusable formal verification models that can be used for verifying a class of designs with predictability ...

Transitioning from Physical to Virtual Automotive Testing Using Virtual ...

Apr 24, 2019 - This Tech Talk presents the use cases and benefits of virtual environments for automotive applications, the components required to establish such an environment, and the current ...

Why is Design Constraints (SDC) Validation Critical at RTL?

Mar 12, 2019 - In this webinar, we will talk about why constraint validation is important at RTL, highlight the different problems, and how designers can solve these problems early in the flow.

Increasing Debug Productivity with Verdi – Today’s Best Practices & Vision ...

Mar 7, 2019 - In this Synopsys webinar, we will show how Verdi helps design verification challenges, improves debug productivity, and give a preview of the future debug technology.

UPF Signoff Using Design Independent Checker

Mar 6, 2019 - This webinar will showcase the latest capabilities for UPF sign-off using the VC UPF methodology.

Addressing Exascale Emulation Debug Complexity – The case for a system-level ...

Feb 27, 2019 - In this webinar, we present how to use ZeBu to cut debug time after a failure has been reported during a multi-billion cycles regression.

An Efficient Hierarchical Verification Flow for Low Power Designs

Feb 21, 2019 - In this webinar, we will cover the benefits of SAM flow, such as the 8X-15X runtime performance gain and reduced memory consumption compared to the full flat verification, all while ...

SpyGlass Early & Often – Lint & CDC for Every Block

Jan 24, 2019 - This SpyGlass webinar explores Lint and CDC as a design problem, not a signoff problem, where early and often is also required.