Verification Resources

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Avoiding SoC Security Threats – What Verification Engineers Should Know

Learn how the Tortuga methodology and products for HSDL together with the Synopsys Verification Continuum® platfrom enable the analysis of security threats for long software scenarios with fast ...

Industry Leaders Present: CXL - Enabling New Capabilities in SoCs

Aug 31, 2021 - Join industry leaders from Synopsys, Intel, Arm, and Astera Labs as they discuss the latest innovations, methodologies and CXL market trends in this series of short webinars.

Pre-empt Late-stage Low Power Issues using Predictive Analysis

Learn how Synopsys’ VC LP enables users with early predictive analysis enabling achievement of significantly shorter design cycle by finding critical low power bugs at the RTL stage rather than at ...

Accelerate Coverage Closure Using VCS’ ML-Driven ICO Technology (Part 2)

In this Synopsys webinar, we will review Synopsys’ new Intelligent Coverage Optimization (ICO) technology, which reduces coverage regression turn-around time (TAT), while maximizing ultimate ...

Accelerate Functional Safety Certification of IP and SoC Designs - Part 2

Jul 20, 2021 - This Synopsys webinar, part two, will provide a deep dive into using VC Formal FUSA to accelerate the fault convergence process.

Accelerate Functional Safety Certification of IP and SoC Designs - Part 1

Jun 22, 2021 - This Synopsys webinar series will cover a high-level introduction to Synopsys FuSa solutions including Z01X and VC Formal that address complex IP challenges.

Using Control Connectivity Checks to Expand Low-Power Signoff

Jun 15, 2021 - Learn custom low power mechanisms using Synopsys VC LP that help capture user intent of complex low power cells control signal connectivity.

Improve Your Software Team’s Productivity and Efficiency with Fast Virtual ...

Jun 10, 2021 - Learn how virtual prototypes can be connected to real and virtual devices to provide the wider environment required to effectively test software.

Successful Strategies to Verify Clock Gating using VC Formal - Part 2

Jun 09, 2021 - By the end of this Synopsys webinar, you will be able to uncover corner case clock gating bugs that are difficult to verify with simulation.

Find and Fix Bugs Early with Correct-by-Construction Coding with Synopsys ...

Jun 02, 2021 - A demonstration of how design and verification iterations can be significantly reduced and major project milestones can be achieved substantially faster using the Synopsys Euclide ...