Verification Resources

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Best Practices for Avoiding Systematic Faults and Handling Random Faults in ...

This 30-minute Webinar reviews the latest methodologies and technologies to efficiently and successfully achieve the functional safety verification targets for semiconductor designs.

Fast Turnaround Time Constraints and Design Guidelines for FPGAs

Oct 7, 2020 - This webinar will highlight Synplify Premier synthesis features such as ‘fast synthesis’, ‘auto constraint’, and ‘continue-on-error’ for early and first-design pass with the fastest ...

Perform Multi-Voltage Checks Faster with Low Power Signoff

Sep 16, 2020 - This webinar will highlight the benefits of tight integration between P&R and low power signoff tools.

Exhaustive Formal Verification of Packet-Based Designs

This webinar presents a case study to verify a packet-based design using the Synopsys VC Formal Property Verification (FPV) app.

Advanced Low Power UPF Design Debug for Faster Signoff

Sep 2, 2020 - In this webinar you will learn how Synopsys’ VC LP helps reduce the debug time drastically with smarter grouping and highlighting of root causes through intelligent analysis and ...

From System to Software: A Study in Efficient, Robust Design for Electric ...

Aug 20, 2020 - In the fast-growing domain of electric vehicle development, many challenges exist. Range anxiety and cost are adoption barriers, in addition to challenges with hardware and software ...

Accelerating High-Frequency Trading with FPGAs – Mike Dini’s Perspective

Aug 6, 2020 - Mike Dini, formerly of the Dini Group, will share his expertise in FPGA hardware and how FPGAs are being used to optimize low- and high-frequency trading (HFT) applications.

Shift Left Control Software Development with Virtual ECU (Japanese)

Shift Left Control Software Development with Virtual ECU

FPGA Prototyping with HAPS-SX VU19P: A More Cost-Effective Choice than ...

Jul 30, 2020 - This webinar will compare and contrast all aspects related to designing, producing and supporting prototyping boards in-house with commercially available FPGA prototyping systems, ...

Avoid Silicon Respins Using RDC Techniques

Jul 23, 2020 - The increasing number of power and reset domains are driving a greater need for reset domain crossing (RDC) analysis. In addition, the RTL quality and embedded software driven ...