Verification Resources

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AI and Formal: A Winning Formula to Accelerate Verification Progress

Jan 27, 2021 - In this Synopsys Webinar, we will explore ML techniques being used in VC Formal Regression Mode Accelerator (RMA) App to accelerate verification progress, improving performance by ...

Virtual Prototyping Next-Gen Automotive Microcontrollers

Dec 10, 2020 - This 30-minute Webinar presents the usage and benefits of virtual prototyping for a wide range of use cases for Infineon’s next-generation AURIXTM TC4xx automotive microcontrollers.

From System to Software: A Study in Efficient, Robust Design for Electric ...

Dec 02, 2020 - This Tech Talk discusses how a unified virtual prototyping solution, which addresses the multi-discipline needs of system, electro-mechanical, and embedded software domains, can help...

How to Accelerate Power-Aware Simulation Debug with Synopsys’ VC LP

Nov 11, 2020 - This presentation demonstrates the benefits of running static checks prior to simulation, enabling simulation users to do quick static checks with Synopsys’ VC LP.

Low Power Verification – Challenges, Methodologies and Flows

Oct 29, 2020 - This Synopsys webinar will highlight how the low power verification challenges can be addressed proficiently by applying a combination of complimentary techniques covering static and...

Writing Structured Testbenches in VHDL

Oct 28, 2020 - Digital designers have been talking about design reuse for 30 years or so. Given that writing the testbench can be as much, if not more, effort than creating the design, testbench ...

Accelerating Validation of Next-Generation Cloud Architectures with Virtual ...

Oct 21, 2020 - In this Synopsys webinar, we will present how a virtual testing solution using Synopsys ZeBu and Keysight IxVerify tester software enables maximizing validation of realistic network ...

Best Practices for Avoiding Systematic Faults and Handling Random Faults in ...

This 30-minute Webinar reviews the latest methodologies and technologies to efficiently and successfully achieve the functional safety verification targets for semiconductor designs.

Fast Turnaround Time Constraints and Design Guidelines for FPGAs

Oct 7, 2020 - This Synopsys webinar will highlight Synplify Premier synthesis features such as ‘fast synthesis’, ‘auto constraint’, and ‘continue-on-error’ for early and first-design pass with the ...

Perform Multi-Voltage Checks Faster with Low Power Signoff

Sep 16, 2020 - This webinar will highlight the benefits of tight integration between P&R and low power signoff tools.