Verification Resources

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AI-enabled Root Cause Analysis for Low Power Verification

Jul 30, 2019 - This webinar will talk about the current application of deterministic and machine learning-based techniques to automatically identify the accurate root-causes for a related group of ...

An Efficient Hierarchical Verification Flow for Low Power Designs

Feb 21, 2019 - In this webinar, we will cover the benefits of SAM flow, such as the 8X-15X runtime performance gain and reduced memory consumption compared to the full flat verification, all while ...

Efficient Low Power Verification and Debug Methodology Using Power Aware ...

Dec 5, 2018 - This webinar will share a methodology for efficient low power verification and debug enabling “shift-left” and ensuring that subtle bugs do not escape to silicon.

Catch Low Power Bugs ASAP – Advanced Static Checking Across the Design Flow ...

Jun 14, 2017 - Learn how the low power static checking and signoff flow with VC LP can help you catch low power bugs ASAP and avoid fatal low power issues.

Accelerated Power Analysis and Verification with Synopsys Verdi Technologies

Nov 8, 2016 - Discover how native integrations of Verdi design debug technologies with Synopsys’ power analysis and verification solutions help catch power-related bugs earlier and faster.

Catch Low-power Simulation Bugs Earlier and Faster with Verdi Power-Aware Debug

Aug 31, 2016 - Learn how Verdi Power-Aware Debug greatly simplifies low-power debug and identifies potential design-killing bugs earlier and faster, with a unified and comprehensive view of the ...