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DVCon India 2019

Sept 25, 2019 - Visit Synopsys at booth #4 and learn more about the Verification Continuum Platoform. You can also see us at the keynote, tutorials or panel discussion.

Harness Architectures: The Link Between Physical and Logical

Aug 21, 2019 - Synopsys SaberES Designer's Harness Architecture accelerates the total design process by using the same databases and automatically combining electrical system design information ...

Synopsys Expands Center of Excellence with Infineon to Deliver Virtualizer ...

Jun 24, 2019 - Expansion of the automotive Center of Excellence collaboration with Infineon to speed development of automotive electronic systems and deliver Synopsys Virtualizer™ Development Kits ...

Simulation for Testing and Analysis of Autonomous Vehicles

Jun 20, 2019 - With the spate of public highway accidents of autonomous vehicles, the conversation has become more intense regarding the need for simulation testing to reduce risky on-road testing ...

Elektrobit and Synopsys Collaborate to Accelerate Automotive Electronic ...

May 13, 2019 - Companies helping to shorten automotive development cycle by enabling transition from physical to virtual system testing.

Transitioning from Physical to Virtual Automotive Testing Using Virtual ...

Apr 24, 2019 - This Tech Talk presents the use cases and benefits of virtual environments for automotive applications, the components required to establish such an environment, and the current ...

Desay SV Standardizes on Synopsys Virtualizer Virtual Prototyping Solutions

Apr 22, 2019 - Desay SV has adopted its Virtualizer™ virtual prototyping solution to accelerate software development of next-generation automotive systems.

Synopsys Establishes Center of Excellence with STMicroelectronics to Speed ...

Apr 18, 2019 - Synopsys collaboration with STMicroelectronics (ST) to establish a Center of Excellence program to speed development of automotive electronic systems and software.

DVCon China 2019

Apr 17, 2019 - Visit Synopsys at booth #106 or catch the keynote, technical short workshops or tutorial.

Joint Optimization of Hardware and Compiler: Modeling AI Accelerators Using ...

This presentation proposes a novel approach for joint optimization of algorithms/compilers and hardware architecture. The top-down/integrated approach that leverages the latest machine learning ...