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Accelerating Software Development for Arm big.LITTLE Processing

Arm and Synopsys describe the benefits of Arm big.LITTLE processing and how Synopsys' Virtualizer Development Kit for Arm Cortex Processors can be used by software developers to optimize the ...

Casual is the New Formal (series)

The Synopsys Verification Group invites you to learn more about Formal Verification, in our new video blog series: Casual is the New Formal. The videos provide an introduction to Formal ...

Customer Highlight - ST Microelectronics

ST meets AMS simulation criteria with VCS-MX and CustomSim - Yuval Shay, Staff Engineer, Mixed-Signal Verification

DAC 2018 Verification Lunch Panel

Jun 26, 2018 - Synopsys hosted a luncheon event at DAC in San Francisco, California. At this event, industry leaders ST, AMD, and Samsung shared their viewpoints on what is driving SoC complexity, ...

Debug Changes At Advanced Nodes

Ribhu Mittal, emulation applications director at Synopsys, zeroes in on what’s changing in debug, including why traditional verification methods are failing in designs with 1 billion gates and a ...

Debugging a USB 3 Linux Driver using Lauterbach TRACE32 and Synopsys ...

This video highlights how Virtualizer enables TRACE32 users to conduct non-intrusive multi-cluster debugging on an Arm® big.LITTLE™ processing system. - Achim Nohl

Debugging Complex PCIe Issues using Synopsys VIP and Verdi Transaction Debug

A Synopsys VIP expert demonstrates the debugging of PCIe 4.0 using Synopsys VIP and Verdi debug at the 2017 PCI-SIG Developers Conference.

Demonstration of the Synopsys Verification IP and Controller IP Core for PCIe...

Marrian Fujinami, Senior AE, demonstrates PCIe 5.0 simulation and debug of the Synopsys VIP and IIP using the Verdi tool at the 2018 PCI-SIG Developers Conference.

Designing an AI SoC

Susheel Tadikonda, VP of networking and storage at Synopsys, looks at how to achieve economies of scale in AI chips and where the common elements are across all the different architectures.

Designing Networking Chips

Susheel Tadikonda, VP of networking and storage at Synopsys, talks about what’s changed in the way networking chips are being designed to deal with a massive increase in data.