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Customer Highlight - ST Microelectronics

ST meets AMS simulation criteria with VCS-MX and CustomSim

Rohde & Schwarz LTE Forum Recap

See the highlights from the LTE showing who attended and what the hot topics were for the LTE community. (Length: 5 mins)

Featured Algorithm Video: Introduction to SPW and the LTE/LTE-A Library

This video provides an insight into the overall structure of the LTE / LTE-A Library, its appearance within the SPW block-diagram based design canvas and its modular structure which allows easy ...

Debug Changes At Advanced Nodes

Ribhu Mittal, emulation applications director at Synopsys, zeroes in on what’s changing in debug, including why traditional verification methods are failing in designs with 1 billion gates and a ...

Designing an AI SoC

Susheel Tadikonda, VP of networking and storage at Synopsys, looks at how to achieve economies of scale in AI chips and where the common elements are across all the different architectures.

Designing Networking Chips

Susheel Tadikonda, VP of networking and storage at Synopsys, talks about what’s changed in the way networking chips are being designed to deal with a massive increase in data.

Formal Datapath Verification

Drill down into how to achieve confidence in datapath designs by applying formal solvers and methods to data transformation areas of a design rather than the control path areas.

Formal Signoff

What’s good enough coverage? What makes one assertion better than another? Find out in this video as well as where the potential holes are in verification.

Signoff-Compatible CDC

Tanveer Singh, senior staff consulting applications engineer at Synopsys, explains why netlist clock domain crossing is replacing RTL CDC at advanced nodes and in AI chips.

UPF-Aware Clock-Domain Crossing

Learn about low-power design techniques at the most advanced process nodes including how to verify the impact of CDC on power at RTL.