Verification Resources

Sort by

Synopsys Suggests

IMS MicroApp Video: Causality Considerations for Multi-Gigabit StatEye Analysis

Mike Heimlich, AWR Corp., Ted Mido and Scott Wedge, Synopsys present "Causality Considerations for Multi-Gigabit StatEye Analysis" as part of the IEEE.tv showcase of MicroApps seminars from the ...

Customer Highlight - ST Microelectronics

ST meets AMS simulation criteria with VCS-MX and CustomSim - Yuval Shay, Staff Engineer, Mixed-Signal Verification

Fundamentals of Virtual Prototypes for Embedded System Development

In this fundamentals course, we will be examining virtual prototypes and some of the impacts they have on delivery schedules, product capabilities, quality and the ease with which multi-processor ...

Verdi3 HW SW Debug Video

This video demonstration shows an overview of the Synopsys Verdi3™ Hardware and Software Debug solution, an instruction-accurate debug solution for SoC designs containing embedded software. ...

Rohde & Schwarz LTE Forum Recap

See the highlights from the LTE showing who attended and what the hot topics were for the LTE community. (Length: 5 mins)

Featured Algorithm Video: Introduction to SPW and the LTE/LTE-A Library

This video provides an insight into the overall structure of the LTE / LTE-A Library, its appearance within the SPW block-diagram based design canvas and its modular structure which allows easy ...

Debug Changes At Advanced Nodes

Ribhu Mittal, emulation applications director at Synopsys, zeroes in on what’s changing in debug, including why traditional verification methods are failing in designs with 1 billion gates and a ...

Designing an AI SoC

Susheel Tadikonda, VP of networking and storage at Synopsys, looks at how to achieve economies of scale in AI chips and where the common elements are across all the different architectures.

Designing Networking Chips

Susheel Tadikonda, VP of networking and storage at Synopsys, talks about what’s changed in the way networking chips are being designed to deal with a massive increase in data.

Formal Datapath Verification

Drill down into how to achieve confidence in datapath designs by applying formal solvers and methods to data transformation areas of a design rather than the control path areas.