What’s good enough coverage? What makes one assertion better than another? Find out in this video as well as where the potential holes are in verification.
Drill down into how to achieve confidence in datapath designs by applying formal solvers and methods to data transformation areas of a design rather than the control path areas.
UPF-Aware Clock-Domain Crossing
Learn about low-power design techniques at the most advanced process nodes including how to verify the impact of CDC on power at RTL.
HAPS-80 Desktop Prototyping Solution Chalk Talk
Aug 16, 2018 - HAPS 80D from Synopsys delivers a complete hardware and software prototyping solution right to your desk. In this episode of Chalk Talk, EE Journal chats with Synopsys about the ...
DAC 2018 Verification Lunch Panel
Jun 26, 2018 - Synopsys hosted a luncheon event at DAC in San Francisco, California. At this event, industry leaders ST, AMD, and Samsung shared their viewpoints on what is driving SoC complexity, ...
Demonstration of the Synopsys Verification IP and Controller IP Core for PCIe...
Marrian Fujinami, Senior AE, demonstrates PCIe 5.0 simulation and debug of the Synopsys VIP and IIP using the Verdi tool at the 2018 PCI-SIG Developers Conference.
SNUG 2018 Verification Lunch Panel: SoC Leaders Verify with Synopsys
Johannes Stahl speaks about the ongoing collaborations between Synopsys and leading SoC companies. David Bural (Texas Instruments) addresses unique verification challenges of embedded processors ...
DVCon 2018 Verification Lunch Panel
Feb 27, 2018 - Synopsys hosted a verification panel at DVCon 2018 that included presentations from Qualcomm and Broadcom as well as an update on the next wave of verification innovation in ...
How Good is Your Next Android SoC? Predict Performance and Power Using Task ...
Get a 30 second preview of a webinar where we review how application workload models, called task graphs, enable designers of Android based systems to capture the processing and communication ...
VC Formal Features for Faster Convergence
Ravindra Aneja, Senior Staff Program Manager at Synopsys, demonstrates some of VC Formal’s key features that enable faster convergence and help with Formal signoff.