Debug Changes At Advanced Nodes
Ribhu Mittal, emulation applications director at Synopsys, zeroes in on what’s changing in debug, including why traditional verification methods are failing in designs with 1 billion gates and a ...
Susheel Tadikonda, VP of networking and storage at Synopsys, looks at how to achieve economies of scale in AI chips and where the common elements are across all the different architectures.
DVCon US 2019 Verification Lunch Panel
Feb 28, 2019 - Industry experts from Arm and NXP share their viewpoints on what is driving SoC complexity, how their teams have achieved success, how you can apply their insights on your next ...
Susheel Tadikonda, VP of networking and storage at Synopsys, talks about what’s changed in the way networking chips are being designed to deal with a massive increase in data.
Jan 30, 2019 - This event is for all HSPICE and FineSim SPICE users and design engineers who want to stay connected with the latest developments in the field of circuit simulation. The evening ...
What’s good enough coverage? What makes one assertion better than another? Find out in this video as well as where the potential holes are in verification.
Drill down into how to achieve confidence in datapath designs by applying formal solvers and methods to data transformation areas of a design rather than the control path areas.
UPF-Aware Clock-Domain Crossing
Learn about low-power design techniques at the most advanced process nodes including how to verify the impact of CDC on power at RTL.
HAPS-80 Desktop Prototyping Solution Chalk Talk
Aug 16, 2018 - HAPS 80D from Synopsys delivers a complete hardware and software prototyping solution right to your desk. In this episode of Chalk Talk, EE Journal chats with Synopsys about the ...
DAC 2018 Verification Lunch Panel
Jun 26, 2018 - Synopsys hosted a luncheon event at DAC in San Francisco, California. At this event, industry leaders ST, AMD, and Samsung shared their viewpoints on what is driving SoC complexity, ...