Verification Resources

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Synopsys Suggests

Debug Changes At Advanced Nodes

Ribhu Mittal, emulation applications director at Synopsys, zeroes in on what’s changing in debug, including why traditional verification methods are failing in designs with 1 billion gates and a ...

SNUG 2019 Verification Lunch Panel

Synopsys hosted a luncheon event at the annual SNUG that highlighted new verification solutions for ZeBu Server 4, HAPS-80 Desktop Prototyping and VC Formal Regression Mode Accelerator App.

DVCon US 2019 Verification Lunch Panel

Industry experts from Arm and NXP share their viewpoints on what is driving SoC complexity, how their teams have achieved success, how you can apply their insights on your next project as well as ...

Designing Networking Chips

Susheel Tadikonda, VP of networking and storage at Synopsys, talks about what’s changed in the way networking chips are being designed to deal with a massive increase in data.

DAC 2018 Verification Lunch Panel

Synopsys hosted a luncheon event at DAC in San Francisco, California. At this event, industry leaders ST, AMD, and Samsung shared their viewpoints on what is driving SoC complexity, how their teams...

SNUG 2018 Verification Lunch Panel: SoC Leaders Verify with Synopsys

Johannes Stahl speaks about the ongoing collaborations between Synopsys and leading SoC companies. David Bural (Texas Instruments) addresses unique verification challenges of embedded processors ...