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DAC 2018 Verification Lunch Panel

Jun 26, 2018 - Synopsys hosted a luncheon event at DAC in San Francisco, California. At this event, industry leaders ST, AMD, and Samsung shared their viewpoints on what is driving SoC complexity, ...

Demonstration of the Synopsys Verification IP and Controller IP Core for PCIe...

Marrian Fujinami, Senior AE, demonstrates PCIe 5.0 simulation and debug of the Synopsys VIP and IIP using the Verdi tool at the 2018 PCI-SIG Developers Conference.

SNUG 2018 Verification Lunch Panel: SoC Leaders Verify with Synopsys

Johannes Stahl speaks about the ongoing collaborations between Synopsys and leading SoC companies. David Bural (Texas Instruments) addresses unique verification challenges of embedded processors ...

Debugging Complex PCIe Issues using Synopsys VIP and Verdi Transaction Debug

Varun Sundaran, Senior CAE, demonstrates the debugging of PCIe Gen4 using Synopsys VIP and Verdi debug at the 2017 PCI-SIG Developers Conference.

SNUG 2017 Verification Lunch Panel: SoC Leaders Verify with Synopsys

On March 22, 2017 Synopsys hosted a luncheon event at the annual Synopsys Users Group (SNUG) event in Santa Clara, CA. At this event, Tom Borgstrom spoke about the ongoing collaborations between ...