Jul 14, 2020 - Native SystemVerilog VIP Features Built-in Coverage, Verification Planning, and Memory-Aware Debug and Performance Analysis
Mar 25, 2020 -Synopsys announces that SiFive, Inc. has selected Synopsys Fusion Design Platform™ and Verification Continuum® platform to enable rapid cloud-based design of next-generation customer ...
Mar 23, 2020 - Synopsys announces VC VIP for Ethernet 800G, based on the Ethernet Technology Consortium (ETC) specification, enabling SoC teams to design networking chips for data centers with ease.
May 30, 2019 - New native tool integrations enable up to 5X higher verification performance.
May 1, 2019 - Synopsys announces the availability of the industry’s first verification IP (VIP) for Non-Volatile Dual In-line Memory Module (NVDIMM-P) for DDR5/4.
Mar 14, 2019 - Native SystemVerilog VIP for USB Features Built-in Coverage, Verification Plan, Protocol-Aware Debug, and Source Code Test Suites
Jan 31, 2018 - Synopsys has collaborated with Arm to deliver the next-generation ACE5 and AXI5 VIP with increased performance for faster verification closure
Oct 05, 2017 - Native SystemVerilog USB VIP Features Built-in Coverage, Verification Plan, Protocol-Aware Debug and Source Code Test Suites
Sep 5, 2017 - Comprehensive Synopsys Platform Enables Accelerated Verification of High-Performance, Low-Power CPU, GPU and System IP for Mobile SoCs
Jun 19, 2017 - Synopsys VIP for the latest AMBA CHI Issue B specification enables customers and partners to extend the standard architecture for their next-generation coherent designs with new ...