Verification Resources

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Achieving Faster Closure using Advanced RTL Static Signoff Platform

Apr 29, 2021 - This Synopsys webinar delves into challenges of a typical static solution as a point tool and how VC SpyGlass RTL signoff solution can help address these challenges.

AI and Formal: A Winning Formula to Accelerate Verification Progress

Jan 27, 2021 - In this Synopsys Webinar, we will explore ML techniques being used in VC Formal Regression Mode Accelerator (RMA) App to accelerate verification progress, improving performance by ...

How to Accelerate Power-Aware Simulation Debug with Synopsys’ VC LP

Nov 11, 2020 - This presentation demonstrates the benefits of running static checks prior to simulation, enabling simulation users to do quick static checks with Synopsys’ VC LP.

Low Power Verification – Challenges, Methodologies and Flows

Oct 29, 2020 - This Synopsys webinar will highlight how the low power verification challenges can be addressed proficiently by applying a combination of complimentary techniques covering static and...

Perform Multi-Voltage Checks Faster with Low Power Signoff

Sep 16, 2020 - This Synopsys webinar will highlight the benefits of tight integration between P&R and low power signoff tools.

Exhaustive Formal Verification of Packet-Based Designs

Sep 14, 2020 - This Synopsys webinar presents a case study to verify a packet-based design using the Synopsys VC Formal Property Verification (FPV) app.

Advanced Low Power UPF Design Debug for Faster Signoff

Sep 2, 2020 - In this Synopsys webinar you will learn how Synopsys’ VC LP helps reduce the debug time drastically with smarter grouping and highlighting of root causes through intelligent analysis ...

Avoid Silicon Respins Using RDC Techniques

Jul 23, 2020 - Explanation of the new RDC methodology that can be used to overcome problems of related analysis.

RISC-V Formal Verification for ISA Compliance

July 7, 2020 - In this webinar, we will present a solution powered by a unique combination of Synopsys VC Formal apps and Axiomise’s RISC-V ISA formal solution enabling fast corner-case bug ...

Avoid Silicon Respins Using RDC Techniques (Chinese)

Jul 01, 2020 - This Synopsys webinar in Chinese will explain these challenges and new RDC methodology that can be used to overcome problems of related analysis.