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Constraints Driven CDC Methodology (Part 3)

Aug 28, 2019 - Part 3 of the webinar series will talk about machine learning-based Root Cause Analysis (RCA) for CDC. Machine learning RCA automatically identifies where to define constraints, ...

AI-enabled Root Cause Analysis for Low Power Verification

Jul 30, 2019 - This webinar will talk about the current application of deterministic and machine learning-based techniques to automatically identify the accurate root-causes for a related group of ...

Constraints Driven CDC Methodology (Part 2)

Jul 17, 2019 - In part 2 of this webinar series, we will discuss how to apply Constraint driven CDC methodology, what are the CDC specific constraints and their semantics and finally how a user can...

Comprehensive Multimode CDC Analysis

Jul 10, 2019 - This webinar will showcase a comprehensive multimode CDC analysis solution using structural and formal methods, where a single set of constraints is applied to analyze the design ...

Constraints Driven CDC Methodology (Part 1)

Jun 26, 2019 - In part 1 of this webinar series, we will discuss how Constraint driven CDC methodology will define and verify the design intent with less chance of missing real RTL bugs.

Using TCL for Clock Domain Crossing Debug

Jun 20, 2019 - This webinar will showcase an alternate way of debugging CDC violations, which allows users to create custom TCL scripts tailored to their flows and methodology, facilitating ...

A Gentle Introduction to Formal Verification

Jun 19, 2019 - The intention of this webinar is to address any concerns and convince the audience that if you're a Designer or a DV engineer, Formal Verification is your new best friend.

Shift left Power Aware Static Verification using CDC and RDC

Jun 13, 2019 - This webinar discusses the verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.

Efficient Formal Verification with Smart Modeling

May 22, 2019 - In this webinar, we will provide insights on how we can build efficient and reusable formal verification models that can be used for verifying a class of designs with predictability ...

Why is Design Constraints (SDC) Validation Critical at RTL?

Mar 12, 2019 - In this webinar, we will talk about why constraint validation is important at RTL, highlight the different problems, and how designers can solve these problems early in the flow.