Verification Resources

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Accelerate Functional Safety Certification of IP and SoC Designs - Part 1

Jun 22, 2021 - This Synopsys webinar series will cover a high-level introduction to Synopsys FuSa solutions including Z01X and VC Formal that address complex IP challenges.

Using Control Connectivity Checks to Expand Low-Power Signoff

Jun 15, 2021 - Learn custom low power mechanisms using Synopsys VC LP that help capture user intent of complex low power cells control signal connectivity.

Successful Strategies to Verify Clock Gating using VC Formal - Part 2

Jun 09, 2021 - By the end of this Synopsys webinar, you will be able to uncover corner case clock gating bugs that are difficult to verify with simulation.

Achieving Faster Closure using Advanced RTL Static Signoff Platform

Apr 29, 2021 - This Synopsys webinar delves into challenges of a typical static solution as a point tool and how VC SpyGlass RTL signoff solution can help address these challenges.

Successful Strategies to Verify Clock Gating using VC Formal - Part 1

Apr 28, 2021 - This Synopsys webinar shares real-life examples of how to execute clock gating verification with a well-defined methodology using the Synopsys VC Formal Sequential Equivalence ...

AI and Formal: A Winning Formula to Accelerate Verification Progress

Jan 27, 2021 - In this Synopsys Webinar, we will explore ML techniques being used in VC Formal Regression Mode Accelerator (RMA) App to accelerate verification progress, improving performance by ...

How to Accelerate Power-Aware Simulation Debug with Synopsys’ VC LP

Nov 11, 2020 - This presentation demonstrates the benefits of running static checks prior to simulation, enabling simulation users to do quick static checks with Synopsys’ VC LP.

Low Power Verification – Challenges, Methodologies and Flows

Oct 29, 2020 - This Synopsys webinar will highlight how the low power verification challenges can be addressed proficiently by applying a combination of complimentary techniques covering static and...

Perform Multi-Voltage Checks Faster with Low Power Signoff

Sep 16, 2020 - This Synopsys webinar will highlight the benefits of tight integration between P&R and low power signoff tools.

Exhaustive Formal Verification of Packet-Based Designs

Sep 14, 2020 - This Synopsys webinar presents a case study to verify a packet-based design using the Synopsys VC Formal Property Verification (FPV) app.