Verification Resources

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VC SpyGlass Lint

The VC SpyGlass Lint provides an integrated solution for analysis, debug, and fixing tied to the RTL description of the design.

VC SpyGlass RDC

VC SpyGlass RDC is built on a VC SpyGlass RTL Signoff platform that provides scalable capacity for quality signoff with high debug productivity.

VC SpyGlass CDC

VC SpyGlass provides a comprehensive methodology with scalable capacity for quality signoff with high debug productivity.

SpyGlass Constraints

Address challenges with a broad-based solution starting early in design process.

SpyGlass CDC

Comprehensive, Low-Noise Clock Domain Crossing Verification

SpyGlass RDC

Comprehensive, Low-Noise Reset Analysis

SpyGlass Power

Complete Solution for Power Optimization at RTL

VC Formal

Next-Generation Formal Verification

SpyGlass Lint

Early Design Analysis for Logic Designers

VC LP

Next-Generation Low Power Static Checking