Verification Resources

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Artificial Intelligence: Let Us Get The Math Right First!

Jun 6, 2019 - Data path verification with formal for artificial intelligence (AI) designs.

Don’t Have A Meltdown Over A Spectre In Your SoC

Mar 7, 2019 - Verifying that there are no bugs in the hardware that cause secure data leaks will help you avoid a meltdown.

Efficient Hierarchical Verification For Low Power Designs

Jan 17, 2019 - This article discusses how tools using new hierarchical verification technologies, such as Synopsys Low Power Verification, enable a “shift-left” in the overall verification TAT and ...

Verifying Clock Domain Crossings in UPF-based Low-power SoCs

Dec 3, 2018 - This article discusses the verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.

Overcoming Low Power Verification Challenges For Mixed-Signal SoC Designs

Oct 11, 2018 - A low power methodology using a combination of static and dynamic verification.

Formal Fundamentals: What’s Hiding Behind Your Constraints

Jul 17, 2018 - The reason we need constraints or assumptions in the first place is to limit the behavior/functionality that the formal tool analyzes to the design’s “legal” states/subset. We don’t ...

Is Verification Falling Behind?

Dec 21, 2017 - It’s becoming harder for tools and methodologies to keep up with increasing design complexity. How to prevent your design from being compromised.

Shifting Left with Static and Formal Verification

Dec 14, 2017 - Static and Formal Verification helps identify RTL issues at their source, pinpoint coding and consistency problems in the RTL descriptions, and help designers resolve issues quickly ...

Using Sequential Equivalence to Verify Clock-Gating Strategies

Nov 6, 2017 - Sequential equivalence checking can be used to show that a block of sequential logic produces the same output for the same inputs after it has been modified by optimization techniques...

Clock Gating Optimization

Sep 21, 2017 - Learn how SpyGlass Power enables RTL power exploration to assist designer in clock gating optimization.