Verification Resources

Sort by

Synopsys Suggests

Efficient Low Power Verification and Debug Methodology Using Power Aware ...

Dec 5, 2018 - This webinar will share a methodology for efficient low power verification and debug enabling “shift-left” and ensuring that subtle bugs do not escape to silicon.

Avoid Silicon Respins with Netlist CDC Verification (Part 2)

Nov 29, 2018 - This webinar will cover the Netlist CDC flow compatible with Static Timing Analysis (STA) and also show a brief demo on the tool capabilities. We will cover a few sample violations ...

Prevent Low Power Bugs Escaping to Silicon with VC LP for Debug

Nov 28, 2018 - This webinar shares techniques for efficient low power debug for simulation, synthesis and prototyping using Synopsys VC LP.

Comprehensive Solution for Reset Domain Crossing Analysis and Signoff (Part 2)

Oct 24, 2018 - This webinar will focus on ways to catch and debug Reset Domain Crossing issues very efficiently and share example scripts for RDC checks. We will also demonstrate some of Synopsys’ ...

Avoid Silicon Respins with Netlist CDC Verification

Oct 3, 2018 - In this webinar, we will talk about how this problem manifests into silicon and the recommended solution for netlist level CDC signoff.

Exhaustive Formal Verification of Packet-Based Designs

Sep 19, 2018 - This webinar presents a case study of verifying a packet-based design using VC Formal Property Checking app (FPV). The crux of the solution is based on abstraction. From the ...

Why Reset Domain Crossing Matters and How It Can Cause Design Respins (Part 1)

Sep 18, 2018 - This webinar focuses on the reset domain crossing problem, how it manifests in designs and pin points the gaps that exist in verification methodology.

Shift Left with Static & Formal Verification: Catching Bugs Early for RTL ...

Dec 6, 2017 - Learn how SpyGlass® Lint Turbo, VC Formal™ Auto Extracted Properties (AEP) and Formal Coverage Analyzer (FCA) Apps identify RTL issues at their source, pinpoints coding and ...

Dealing with Inconclusive Formal Proofs

Dec 1, 2017 – This webinar explores practical ways of dealing with inconclusive formal proofs when using VC Formal, including the use of complexity analysis and bounded reachability analysis, ...

Understanding Clock-Gating Metrics: RTL Power Exploration with SpyGlass Power

Sep 13, 2017 - In this webinar, we will show how designers can use SpyGlass Power to explore the design for early power, analyze the clock gating efficiency across multiple scenarios and make ...