Jun 19, 2019 - The intention of this webinar is to address any concerns and convince the audience that if you're a Designer or a DV engineer, Formal Verification is your new best friend.
Jun 13, 2019 - This webinar discusses the verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.
May 22, 2019 - In this webinar, we will provide insights on how we can build efficient and reusable formal verification models that can be used for verifying a class of designs with predictability ...
Mar 12, 2019 - In this webinar, we will talk about why constraint validation is important at RTL, highlight the different problems, and how designers can solve these problems early in the flow.
Mar 6, 2019 - This webinar will showcase the latest capabilities for UPF sign-off using the VC UPF methodology.
Feb 21, 2019 - In this webinar, we will cover the benefits of SAM flow, such as the 8X-15X runtime performance gain and reduced memory consumption compared to the full flat verification, all while ...
Jan 24, 2019 - This SpyGlass webinar explores Lint and CDC as a design problem, not a signoff problem, where early and often is also required.
Dec 5, 2018 - This webinar will share a methodology for efficient low power verification and debug enabling “shift-left” and ensuring that subtle bugs do not escape to silicon.
Nov 29, 2018 - This webinar will cover the Netlist CDC flow compatible with Static Timing Analysis (STA) and also show a brief demo on the tool capabilities. We will cover a few sample violations ...
Nov 28, 2018 - This webinar shares techniques for efficient low power debug for simulation, synthesis and prototyping using Synopsys VC LP.