Find SoC bugs earlier and faster, bring-up software earlier, validate the entire system, verification
Next-generation static verification and formal verification solutions to find bugs earlier in the design cycle and accelerate root cause analysis.
Synopsys SpyGlass provides insight about designs early in the process at RTL, enabling efficient verification and optimization of SoC designs.
Synopsys SpyGlass Lint is an integrated solution for early design analysis with the most in-depth analysis at the RTL design phase.
Synopsys SpyGlass CDC provides comprehensive, low-noise clock domain crossing verification for design-and-debug CDC issues.
Synopsys SpyGlass RDC (Reset Domain Crossing) provides comprehensive, low-noise reset analysis verification.
Synopsys SpyGlass Power provides a complete solution for power optimization at RTL with reduced static and dynamic consumption.
SpyGlass for FPGA provides a solution for early design analysis with asynchronous clock domain crossing analysis at the RTL design phase.
The VC LP static low power verification solution includes over 400 checks and performance for next generation low power static checking.VC LP (VC Low Power) is a multi-voltage low power static rule...
VC Formal is the next-generation formal verification solution that has the capacity, speed and flexibility to verify difficult SoC design challenges.