Verification Resources

Sort by

Synopsys Suggests

Overcoming Low Power Verification Challenges For Mixed-Signal SoC Designs

Oct 11, 2018 - A low power methodology using a combination of static and dynamic verification.

Formal Fundamentals: What’s Hiding Behind Your Constraints

Jul 17, 2018 - The reason we need constraints or assumptions in the first place is to limit the behavior/functionality that the formal tool analyzes to the design’s “legal” states/subset. We don’t ...

Is Verification Falling Behind?

Dec 21, 2017 - It’s becoming harder for tools and methodologies to keep up with increasing design complexity. How to prevent your design from being compromised.

Shifting Left with Static and Formal Verification

Dec 14, 2017 - Static and Formal Verification helps identify RTL issues at their source, pinpoint coding and consistency problems in the RTL descriptions, and help designers resolve issues quickly ...

Using Sequential Equivalence to Verify Clock-Gating Strategies

Nov 6, 2017 - Sequential equivalence checking can be used to show that a block of sequential logic produces the same output for the same inputs after it has been modified by optimization techniques...

Clock Gating Optimization

Sep 21, 2017 - Learn how SpyGlass Power enables RTL power exploration to assist designer in clock gating optimization.

Eight Tips for Performing Effective Unreachability Analysis

Apr 26, 2017 - One popular application of formal verification techniques is to automatically detect ‘dead’ code, a process known as unreachability analysis.

The Art of Abstraction

Mar 9, 2017 - The key to successful abstraction in formal verification is to consider what functionality needs to be verified and at what level of detail, and then to abstract areas of the design ...

Are You Formally Connected?

Jan 18, 2017 - A large SoC has tens of thousands of connections between modules and pins. Checking that these connections have been made properly is an important step in the verification process. ...

Exploiting the power of reset in formal verification

Mar 1, 2016 - The reset state of a module or SoC that is being verified can have a huge impact on the scope and correctness of the verification. When using simulation for verification, the reset ...