Verification Resources

Sort by

Synopsys Suggests

Faster Verification Closure from IP to SoC Using the Verification Continuum ...

Dec 4, 2019 - The webinar delves into how the Synopsys end-to-end verification strategy scales from IP-level functional verification to full system-level validation & performance analysis using ...

Defining Timing Constraints using SDC

Sep 11, 2019 - This webinar will help you get started with building timing constraints for your digital design using the industry standard Synopsys Timing Constraints (SDC) format.

Efficient Low Power Verification and Debug Methodology Using Power Aware ...

Dec 5, 2018 - This webinar will share a methodology for efficient low power verification and debug enabling “shift-left” and ensuring that subtle bugs do not escape to silicon.

Time-travel in a SystemVerilog/UVM World--Interactive Testbench Debug Unleashed!

Jul 20, 2016 - Learn how interactive debug is ushering in a new era in testbench debug.