Verification Resources

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Defining Timing Constraints using SDC

Sep 11, 2019 - This webinar will help you get started with building timing constraints for your digital design using the industry standard Synopsys Timing Constraints (SDC) format.

Efficient Low Power Verification and Debug Methodology Using Power Aware ...

Dec 5, 2018 - This webinar will share a methodology for efficient low power verification and debug enabling “shift-left” and ensuring that subtle bugs do not escape to silicon.

Accurate Power Analysis Earlier & Faster – Using Synopsys PowerReplay and ...

Jun 01, 2017 - Learn how PowerReplay and PrimeTime PX enable SoC designers to make timely optimizations to achieve power targets accurate to within 5% of power signoff.

Cut Your Simulation Runtime in Half (and More!) – Adopting and Using VCS ...

Feb 21, 2017 - Learn about Synopsys' breakthrough Cheetah Fine-Grained Parallelism (FGP) simulation technology that enables significant performance gains without design changes or VCS simulation ...

Become an SVA Expert in One Hour

Jan 17, 2017 - In this webinar, Doulos CTO John Aynsley teaches the core principles necessary to understand and use SystemVerilog Assertions, focussing on the aspects of SVA that are applicable to ...

Time-travel in a SystemVerilog/UVM World--Interactive Testbench Debug Unleashed!

Jul 20, 2016 - Learn how interactive debug is ushering in a new era in testbench debug.