Jul 16, 2019 - Most chip designs now employ low-power design techniques, making accurate estimates of power consumption necessary.
Jun 18, 2019 - Learn about power management for both chip verification and implementation, the emerging importance of pre-RTL UPF checks and the scalability of UPF for large designs.
May 30, 2019 - How to use UPF information model APIs to write re-usable low power testbenches that can monitor and control UPF objects.
Jan 17, 2019 - This article discusses how tools using new hierarchical verification technologies, such as Synopsys Low Power Verification, enable a “shift-left” in the overall verification TAT and ...
Dec 13, 2018 - This article discusses using the capabilities of a power aware simulator coupled with an intuitive and powerful debug to ensure that subtle bugs do not escape silicon.
Dec 3, 2018 - This article discusses the verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.
Oct 11, 2018 - A low power methodology using a combination of static and dynamic verification.
May 10, 2018 - Why modeling power much earlier has suddenly become so critical for so many applications.
Sep 7, 2017 - Creating accurate models for Wide Band Gap (WBG) power devices representing their complete behavior is vital to the system simulation for ensuring that the simulation results are ...
Sep 8, 2016 - From initial concepts to final sign-off, power has become one of the most challenging design problems.