Jul 16, 2019 - Most chip designs now employ low-power design techniques, making accurate estimates of power consumption necessary.
Jun 18, 2019 - Learn about power management for both chip verification and implementation, the emerging importance of pre-RTL UPF checks and the scalability of UPF for large designs.
May 30, 2019 - How to use UPF information model APIs to write re-usable low power testbenches that can monitor and control UPF objects.
Jan 17, 2019 - This article discusses how tools using new hierarchical verification technologies, such as Synopsys Low Power Verification, enable a “shift-left” in the overall verification TAT and ...
Dec 13, 2018 - This article discusses using the capabilities of a power aware simulator coupled with an intuitive and powerful debug to ensure that subtle bugs do not escape silicon.
Dec 03, 2018 - This article discusses the verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.
Oct 11, 2018 - A low power methodology using a combination of static and dynamic verification.
Feb 15, 2016 - Demand is increasing for consistency in power modeling, but it has taken far longer than anyone would have guessed.
Feb 11, 2016 - A new version of IEEE 1801 enables complete power-aware flows to be constructed using a meet-in-the-middle concept. What will it mean to you and what new parts of the flow will it ...