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Accurate Power Analysis Using Real Software Workloads

Jul 16, 2019 - Most chip designs now employ low-power design techniques, making accurate estimates of power consumption necessary.

Synopsys Low Power Workshop Offers Breadth and Depth

Jun 18, 2019 - Learn about power management for both chip verification and implementation, the emerging importance of pre-RTL UPF checks and the scalability of UPF for large designs.

Artificial Intelligence: Let Us Get The Math Right First!

Jun 6, 2019 - Data path verification with formal for artificial intelligence (AI) designs.

Shift-Left Low Power Verification With UPF Information Model

May 30, 2019 - How to use UPF information model APIs to write re-usable low power testbenches that can monitor and control UPF objects.

Exascale Emulation Debug Challenges

Apr 11, 2019 - Learn how to address the 3 primary verification challenges of complex SoCs: reducing the effort to find the time window around the root cause of a test failure, reproducing the root ...

Efficient Hierarchical Verification For Low Power Designs

Jan 17, 2019 - This article discusses how tools using new hierarchical verification technologies, such as Synopsys Low Power Verification, enable a “shift-left” in the overall verification TAT and ...

Efficient Low Power Verification & Debug Methodology Using Power-Aware ...

Dec 13, 2018 - This article discusses using the capabilities of a power aware simulator coupled with an intuitive and powerful debug to ensure that subtle bugs do not escape silicon.

Verifying Clock Domain Crossings in UPF-based Low-power SoCs

Dec 3, 2018 - This article discusses the verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.

Overcoming Low Power Verification Challenges For Mixed-Signal SoC Designs

Oct 11, 2018 - A low power methodology using a combination of static and dynamic verification.

Improving EMI Performance Through Simulation

Sep 12, 2018 - Here's a method for improving EMI performance through simulation during the product design phase. This will ultimately reduce the cost of hardware verification and improve productivity.