Verification Resources

Sort by

Synopsys Suggests

ARM and Synopsys Collaborate On ARM Cortex-A72 Processor-based SoCs with IC ...

Feb 06, 2015 - ARM and Synopsys Collaboration Enables Optimized Implementation of ARM Cortex-A72 Processor-based SoCs with IC Compiler II

Synopsys’ New 25G/50G Ethernet Verification IP Enables Next-Generation ...

Feb 03, 2015 - Native SystemVerilog Ethernet VIP and Source Code Test Suites Enhanced with Built-in-Coverage and Support for Protocol-aware Debug

Synopsys Enables Continuous Debug Innovation with More Than 200 VC Apps Now ...

Mar 17, 2015 - Synopsys how has more than 200 debug and analysis apps available on the VC Apps Exchange portal and in the Verdi® VC Apps Toolbox, demonstrating rapid momentum for customized ...

Synopsys' New HAPS-80 FPGA-Based Prototyping Solution Delivers Up to 100 MHz ...

Sep 16, 2015 - Integrated HAPS Hardware and ProtoCompiler Software Reduces Time to First Prototype to Less than Two Weeks

Synopsys Delivers Unified Analog and Mixed-Signal Debug with Verdi Advanced ...

Feb 23, 2016 - Extends Verdi's Market-Leading SoC Debug Platform with Comprehensive and Automated AMS Debug Capabilities

Debug Becomes A Bigger Problem

Feb 11, 2016 - EDA companies have been developing more integrated debug flows that bring execution engines and hardware and software closer together, but is that enough?

Debug: Last Bastion Of Automation

Jan 27, 2016 - Folklore erroneously claims verification consumes 70% of development time. But does debug really consume 50%?

Gaps In Performance, Power Coverage

Oct 15, 2015 - Coverage tells us when we have done enough functional verification, but what about power and performance? How do you know you have found the worst case?

Verdi3 HW SW Debug Video

This video demonstration shows an overview of the Synopsys Verdi3™ Hardware and Software Debug solution, an instruction-accurate debug solution for SoC designs containing embedded software. ...

Preparing for Low-Power Verification Success: Setting Objectives and ...

Oct 8, 2015 - Functionally verifying complex SoCs is an enormous challenge, and the challenge grows when multiple power domains are throttled or powered up and down for power management needs.