Verification Resources

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Verdi Transaction Debug Solution

In this white paper we will discuss the different challenges of interconnect with multi master slave configuration in AXI_ACE and how debug solutions can help verification engineer to find these ...

Analyzing Testbench Design Performance Using Verdi Performance Analyzer

This paper describes the challenge to measure design performance and explains how Verdi performance Analyzer enables run time performance analysis to help achieve desired chip performance. - ...

Verdi Transaction Debug Platform: A Simplified Way to Debug IIP Designs and SoC

This white paper describes the concept of debugging with “real time dump” using Verdi Transaction Debug Platform (Protocol Analyzer, nWave, nTrace). - May 2018

Measuring and Analyzing SoC Performance with Verdi Performance Analyzer

Measure and Analyze SoC Performance with Verdi Performance Analyzer using VIP and HBM (High Bandwidth Memory) technology and controllers. - May 2018

Enabling Synchronized Hardware Software Debug with Verdi³

Verdi³™ HW SW Debug is an instruction-accurate embedded processor debug solution that offers fully synchronized views between hardware, as RTL or gate-level design models, and software, as C or ...

Transaction Debug with Verdi

SoC design is complex. It involves both software and hardware design that calls for a higher level of abstraction to ensure accurate verification. Transaction-level verification and debug offers ...

Rethinking SoC Verification

The industry is at an inflection point that calls for new, integrated verification solutions that will offer a fundamental shift forward in productivity, performance, capacity and functionality. ...