Verification Resources

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Exascale Emulation Debug Challenges

Apr 11, 2019 - Learn how to address the 3 primary verification challenges of complex SoCs: reducing the effort to find the time window around the root cause of a test failure, reproducing the root ...

Synopsys Tackles Debug for Giga-Runs on Giga-Designs

Mar 12, 2019 - This article explains exascale debug and how the Synopsys ZeBu emulation system can cut debug time after a failure has been reported during a multi-billion cycles regression.

Efficient Low Power Verification & Debug Methodology Using Power-Aware ...

Dec 13, 2018 - This article discusses using the capabilities of a power aware simulator coupled with an intuitive and powerful debug to ensure that subtle bugs do not escape silicon.

Debug Issues Grow At New Nodes

Jul 26, 2018 - Finding the root cause of problems becoming more difficult as systemic complexity rises; methodology and different approaches play an increasingly important role.

Bottlenecks be Gone - Automated Performance Verification with Synopsys

Feb 15, 2018 - Perform automated end-to-end performance verification using Synopsys VC VIP AutoPerformance, Verdi Performance Analyzer and Verdi Protocol Analyzer.

Shifting Left with Static and Formal Verification

Dec 14, 2017 - Static and Formal Verification helps identify RTL issues at their source, pinpoint coding and consistency problems in the RTL descriptions, and help designers resolve issues quickly ...

Synopsys at DVCon 2016

Feb 23, 2016 - DVCon starts on Monday Feb 29th and as always should be a packed event. One of the most obvious things you will notice is Synopsys’ presence in the exhibit hall – they take up a ...

Debug Becomes A Bigger Problem

Feb 11, 2016 - EDA companies have been developing more integrated debug flows that bring execution engines and hardware and software closer together, but is that enough?

Debug: Last Bastion Of Automation

Jan 27, 2016 - Folklore erroneously claims verification consumes 70% of development time. But does debug really consume 50%?

Reachable or reached, covered or coverable – is it just semantics?

Jan 19, 2016 - RTL code coverage is used to measure the progress of SoC functional verification for simulation, formal property verification (FPV) and other formal techniques, but have you ever ...