Verification Resources

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Synopsys Suggests

Synopsys Low Power Workshop Offers Breadth and Depth

Jun 18, 2019 - Learn about power management for both chip verification and implementation, the emerging importance of pre-RTL UPF checks and the scalability of UPF for large designs.

Artificial Intelligence: Let Us Get The Math Right First!

Jun 6, 2019 - Data path verification with formal for artificial intelligence (AI) designs.

Shift-Left Low Power Verification With UPF Information Model

May 30, 2019 - How to use UPF information model APIs to write re-usable low power testbenches that can monitor and control UPF objects.

Exascale Emulation Debug Challenges

Apr 11, 2019 - Learn how to address the 3 primary verification challenges of complex SoCs: reducing the effort to find the time window around the root cause of a test failure, reproducing the root ...

Synopsys Tackles Debug for Giga-Runs on Giga-Designs

Mar 12, 2019 - This article explains exascale debug and how the Synopsys ZeBu emulation system can cut debug time after a failure has been reported during a multi-billion cycles regression.

Don’t Have A Meltdown Over A Spectre In Your SoC

Mar 7, 2019 - Verifying that there are no bugs in the hardware that cause secure data leaks will help you avoid a meltdown.

Accelerate SSD Software Development And System Validation

Feb 28, 2019 - Start development early on the complex firmware required by next generation SSDs.

Efficient Hierarchical Verification For Low Power Designs

Jan 17, 2019 - This article discusses how tools using new hierarchical verification technologies, such as Synopsys Low Power Verification, enable a “shift-left” in the overall verification TAT and ...

Efficient Low Power Verification & Debug Methodology Using Power-Aware ...

Dec 13, 2018 - This article discusses using the capabilities of a power aware simulator coupled with an intuitive and powerful debug to ensure that subtle bugs do not escape silicon.

Verifying Clock Domain Crossings in UPF-based Low-power SoCs

Dec 3, 2018 - This article discusses the verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.