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Efficient Hierarchical Verification For Low Power Designs

Jan 17, 2019 - This article discusses how tools using new hierarchical verification technologies, such as Synopsys Low Power Verification, enable a “shift-left” in the overall verification TAT and ...

Efficient Low Power Verification & Debug Methodology Using Power-Aware ...

Dec 13, 2018 - This article discusses using the capabilities of a power aware simulator coupled with an intuitive and powerful debug to ensure that subtle bugs do not escape silicon.

Verifying Clock Domain Crossings in UPF-based Low-power SoCs

Dec 3, 2018 - This article discusses the verification challenges of using low-power design techniques to enable advanced power-management strategies in complex SoCs.

Overcoming Low Power Verification Challenges For Mixed-Signal SoC Designs

Oct 11, 2018 - A low power methodology using a combination of static and dynamic verification.

Improving EMI Performance Through Simulation

Sep 12, 2018 - Here's a method for improving EMI performance through simulation during the product design phase. This will ultimately reduce the cost of hardware verification and improve productivity.

SaberRD: Ingeteam Interview by Powersys

Sep 11, 2018 - Powersys had the chance to interview Alain Sanchez, IMD-Industrial & Marine Drives, Product Technician at Ingeteam. In this interview, Alain discusses the benefits of using SaberRD ...

Architecting an ML Design

Aug 14, 2018 - Learn how hardware design methods can advance building machine learning systems.

Verification Engineers Embrace Emulation for the Shift Left

Jul 27, 2018 - At a panel session at DAC, Synopsys customers talked about some of the ways they make verification more efficient and bring technologies such as formal, emulation, and simulation ...

Debug Issues Grow At New Nodes

Jul 26, 2018 - Finding the root cause of problems becoming more difficult as systemic complexity rises; methodology and different approaches play an increasingly important role.

Formal Fundamentals: What’s Hiding Behind Your Constraints

Jul 17, 2018 - The reason we need constraints or assumptions in the first place is to limit the behavior/functionality that the formal tool analyzes to the design’s “legal” states/subset. We don’t ...