Feb 11, 2016 - EDA companies have been developing more integrated debug flows that bring execution engines and hardware and software closer together, but is that enough?
Jan 27, 2016 - Folklore erroneously claims verification consumes 70% of development time. But does debug really consume 50%?
Oct 15, 2015 - Coverage tells us when we have done enough functional verification, but what about power and performance? How do you know you have found the worst case?
Oct 8, 2015 - Functionally verifying complex SoCs is an enormous challenge, and the challenge grows when multiple power domains are throttled or powered up and down for power management needs.
Jan 19, 2016 - RTL code coverage is used to measure the progress of SoC functional verification for simulation, formal property verification (FPV) and other formal techniques, but have you ever ...
Jul 26, 2018 - Finding the root cause of problems becoming more difficult as systemic complexity rises; methodology and different approaches play an increasingly important role.
Dec 13, 2018 - This article discusses using the capabilities of a power aware simulator coupled with an intuitive and powerful debug to ensure that subtle bugs do not escape silicon.
Apr 11, 2019 - Learn how to address the 3 primary verification challenges of complex SoCs: reducing the effort to find the time window around the root cause of a test failure, reproducing the root ...
Feb 15, 2018 - Perform automated end-to-end performance verification using Synopsys VC VIP AutoPerformance, Verdi Performance Analyzer and Verdi Protocol Analyzer.
Nov 3, 2015 - Michael Sanie, Senior Director Marketing in the Synopsys Verification Group, gave the wrap-up presentation at SpyGlass World recently, on the Synopsys Verification Direction.