Dec 13, 2018 - This article discusses using the capabilities of a power aware simulator coupled with an intuitive and powerful debug to ensure that subtle bugs do not escape silicon.
Jul 26, 2018 - Finding the root cause of problems becoming more difficult as systemic complexity rises; methodology and different approaches play an increasingly important role.
Feb 15, 2018 - Perform automated end-to-end performance verification using Synopsys VC VIP AutoPerformance, Verdi Performance Analyzer and Verdi Protocol Analyzer.
Dec 14, 2017 - Static and Formal Verification helps identify RTL issues at their source, pinpoint coding and consistency problems in the RTL descriptions, and help designers resolve issues quickly ...
Feb 23, 2016 - DVCon starts on Monday Feb 29th and as always should be a packed event. One of the most obvious things you will notice is Synopsys’ presence in the exhibit hall – they take up a ...
Feb 11, 2016 - EDA companies have been developing more integrated debug flows that bring execution engines and hardware and software closer together, but is that enough?
Jan 27, 2016 - Folklore erroneously claims verification consumes 70% of development time. But does debug really consume 50%?
Jan 19, 2016 - RTL code coverage is used to measure the progress of SoC functional verification for simulation, formal property verification (FPV) and other formal techniques, but have you ever ...
Nov 3, 2015 - Michael Sanie, Senior Director Marketing in the Synopsys Verification Group, gave the wrap-up presentation at SpyGlass World recently, on the Synopsys Verification Direction.
Oct 15, 2015 - Coverage tells us when we have done enough functional verification, but what about power and performance? How do you know you have found the worst case?