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Extending Digital Verification Techniques for Mixed-Signal SoCs with VCS AMS

The VCS AMS mixed-signal verification solution extends proven digital verification techniques to mixed-signal designs to deliver high-quality verification coverage of complex mixed-signal SoCs. - ...

FinFET Technology – Understanding and Productizing a New Transistor From TSMC...

This white paper discusses the major challenges with FinFETs and how TSMC has been collaborating with Synopsys, one of their ecosystem partners, to deliver a complete solution. Key elements of this...

MOS Device Aging Analysis with HSPICE and CustomSim

MOS Reliability Analysis (MOSRA) in HSPICE and CustomSim offers a robust and economic alternative to empirical overdesign and extensive lifetime testing. - Bogdan Tudor, Joddy Wang, Weidong Liu, ...

Automated Regression for Mixed-Signal Verification

CustomExplorer™ Ultra represents the next generation in mixed-signal verification environment, including regression management, debug and analysis for complex SoC design. - Duncan McDonald, Product...

Using Digital Verification Techniques on Mixed-signal SoCs with CustomSim and...

A case study that explains the various aspects of a scalable and reusable methodology for verifying analog IP that can be applied to VMM/UVM, from verification planning to testbench implementation ...

Accelerating Analog Simulation with HSPICE Precision Parallel Technology

HSPICE Precision Parallel technology is a new multicore transient simulation extension to HSPICE for both pre- and post-layout of complex analog circuits such as PLLs, ADCs, DACs, SERDES, and other...

Utilizing Digital Techniques for Analog and Mixed-Signal Verification

The ability of CustomSim to co-simulate with Synopsys’ VCS digital simulator opens up the possibility of a “best of both worlds” approach enabling the majority of the chip to be simulated in the ...

Extraction Techniques for High-performance, High-capacity Simulation

Today’s advanced process technologies and faster time-to-market schedules are pushing the limits of verification tools. Post-layout simulation runtimes are increasing 2-4x with every new process ...

PLL Noise Analysis with HSPICE RF

This white paper describes a procedure for efficiently extracting key noise measurements for a phase locked loop using HSPICE RF. The procedure has been updated to take advantage of several new and...