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Solving the ASIC Prototype Partition Problem with Synopsys ProtoCompiler

When developing a multi-FPGA prototype of an ASIC or SOC, you have many decisions to make: how to distribute clocks; where to put the daughter boards with real-world interfaces; which modules ...

Advanced Power and Performance Optimization for Multicore SoCs

The Multicore Optimization (MCO) technology in Synopsys Platform Architect provides an environment for early exploration and optimization of complex Multicore SoC (MP-SoC) platforms. It allows ...

Rethinking SoC Verification

The industry is at an inflection point that calls for new, integrated verification solutions that will offer a fundamental shift forward in productivity, performance, capacity and functionality. ...

Virtual Hardware "In-the-Loop": Earlier Testing for Automotive Applications ...

This whitepaper is the first one in a series of publications that will describe the concept of virtual hardware "in-the-loop" (vHIL). The goal of vHIL is to frontload the testing process by ...

Using Virtual Prototypes to Address the Growing Software Complexity in ...

This white paper explores how using virtual prototypes to model microcontrollers and electronic control units provide multiple benefits across the automotive supply chain. These include but are not...

FinFET Technology – Understanding and Productizing a New Transistor From TSMC...

This white paper discusses the major challenges with FinFETs and how TSMC has been collaborating with Synopsys, one of their ecosystem partners, to deliver a complete solution. Key elements of this...

Virtual Prototypes: When, Where And How To Use Them

An innovation-hungry public and a highly competitive marketplace make for short product cycles, while the sophistication and performance expected of digital devices grows with every new product ...

Designing the Right Architecture

In this white paper, we present a tool-assisted system-level performance analysis flow for interconnect and memory performance optimization using Synopsys Platform Architect. This environment ...

Methods and Tools for Bring-Up and Debug of an FPGA-Based ASIC Prototype

Software simulation of RTL is no longer capable of providing all of the verification required for today's complex ASIC designs. Modern ASICs are a complex mixture of hardware and software, so it is...

Discovery Verification IP

New Generation of VIP to Address the Growing Challenge of Complex Protocol and SoC Verification. - Neill Mullinger, Synopsys - February, 2012