Verification Resources

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11 Myths About SoC/ASIC/FPGA Resets

Jun 03, 2021 - Learn what a reset domain crossing is, the best way to verify resets, and the role of static reset analysis.

Accelerated Verification with Synopsys

Jul 17, 2018 - At DAC 2018, Synopsys held a lunch panel discussing verification challenges faced by the industry leaders, their adopted approaches and the overall verification technology trends.

Architecting an ML Design

Aug 14, 2018 - Learn how hardware design methods can advance building machine learning systems.

Synopsys Tackles Debug for Giga-Runs on Giga-Designs

Mar 12, 2019 - This article explains exascale debug and how the Synopsys ZeBu emulation system can cut debug time after a failure has been reported during a multi-billion cycles regression.