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Fast Turnaround Time Constraints and Design Guidelines for FPGAs

Oct 7, 2020 - This Synopsys webinar will highlight Synplify Premier synthesis features such as ‘fast synthesis’, ‘auto constraint’, and ‘continue-on-error’ for early and first-design pass with the ...

Perform Multi-Voltage Checks Faster with Low Power Signoff

Sep 16, 2020 - This webinar will highlight the benefits of tight integration between P&R and low power signoff tools.

Exhaustive Formal Verification of Packet-Based Designs

This webinar presents a case study to verify a packet-based design using the Synopsys VC Formal Property Verification (FPV) app.

Formal Verification Becoming Critical To Auto Security, Safety

Sep 09, 2020 - Formal verification is poised to take on an increasingly significant role in automotive security, building upon its already widespread use in safety-critical applications.

Advanced Low Power UPF Design Debug for Faster Signoff

Sep 2, 2020 - In this webinar you will learn how Synopsys’ VC LP helps reduce the debug time drastically with smarter grouping and highlighting of root causes through intelligent analysis and ...

From System to Software: A Study in Efficient, Robust Design for Electric ...

Aug 20, 2020 - In the fast-growing domain of electric vehicle development, many challenges exist. Range anxiety and cost are adoption barriers, in addition to challenges with hardware and software ...

NSITEXE Adopts Synopsys HAPS Prototyping to Validate Data Flow Processor IP

August 19, 2020 - Synopsys announced that NSITEXE adopted Synopsys HAPS®-80 prototyping solution to develop their current and next-generation Data Flow Processor (DFP) IP portfolio.

Verifying Safety-Critical FPGA Designs with Fault Simulation

This white paper focuses on the use of FPGAs for safety-critical designs and how they can be verified to meet functional safety requirements. Fault simulation plays a key role in this process. - ...

Early Verification of Multi-Cycle Paths and False Paths in Simulation

This white paper focuses on false paths and multi-cycle paths, the use of Synopsys Design Constraints (SDC) to specify these exceptions, and the “shift left” of verification from full-timing ...

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