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SaberRD Training Video 13 - Worst-Case Analysis

This video shows how Saber’s Worst-Case Analysis identifies combinations of component parameters and operating conditions that diminish performance. Addressing these worst-case corners creates a ...

SaberRD Training Video 14 - Fault Analysis

This video explains how Saber’s fault simulation and automation are ISO 26262 certified and provide an approach that is faster and more comprehensive than manual fault-tracing methods.

SaberRD Training Video 15 - Stress Analysis

Analyzing and addressing over-stress on components creates a robust design. Saber’s Stress Analysis automates the process with a few simple steps.

Signoff-Compatible CDC

Tanveer Singh, senior staff consulting applications engineer at Synopsys, explains why netlist clock domain crossing is replacing RTL CDC at advanced nodes and in AI chips.

Debug Changes At Advanced Nodes

Ribhu Mittal, emulation applications director at Synopsys, zeroes in on what’s changing in debug, including why traditional verification methods are failing in designs with 1 billion gates and a ...

SNUG 2019 Verification Lunch Panel

Synopsys hosted a luncheon event at the annual SNUG that highlighted new verification solutions for ZeBu Server 4, HAPS-80 Desktop Prototyping and VC Formal Regression Mode Accelerator App.

Designing an AI SoC

Susheel Tadikonda, VP of networking and storage at Synopsys, looks at how to achieve economies of scale in AI chips and where the common elements are across all the different architectures.

DVCon US 2019 Verification Lunch Panel

Industry experts from Arm and NXP share their viewpoints on what is driving SoC complexity, how their teams have achieved success, how you can apply their insights on your next project as well as ...

Designing Networking Chips

Susheel Tadikonda, VP of networking and storage at Synopsys, talks about what’s changed in the way networking chips are being designed to deal with a massive increase in data.


This event is for all HSPICE and FineSim SPICE users and design engineers who want to stay connected with the latest developments in the field of circuit simulation. The evening starts with a ...