Verification Resources

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Formal Verification Becoming Critical To Auto Security, Safety

Sep 09, 2020 - Formal verification is poised to take on an increasingly significant role in automotive security, building upon its already widespread use in safety-critical applications.

Making Sure AI/ML Works In Test Systems

Mar 09, 2021 - Artificial intelligence and machine learning is being utilized increasingly to find patterns and outlier data in chip manufacturing and test, improving the overall yield and ...

Overcoming Low Power Verification Challenges For Mixed-Signal SoC Designs

Oct 11, 2018 - A low power methodology using a combination of static and dynamic verification.

Requirements For Exhaustive SoC Reset Domain Crossing Checks

Apr 13, 2021 - There are many requirements for RDC checks to be effective, and these must be considered seriously by any engineer looking to select a commercial solution for reset verification.

Scaling Simulation

May 27, 2021 - Design sizes have increased by orders of magnitude while design times have shrunk, pointing to simulation remaining a suitable tool for the job.

Shift-Left Low Power Verification With UPF Information Model

May 30, 2019 - How to use UPF information model APIs to write re-usable low power testbenches that can monitor and control UPF objects.

Silo Busting In The Design Flow

Nov 24, 2020 - Learn more about how Waterfall development flows no longer work for chip design, but unified tool flows may not be the answer.

Virtual Prototyping For Power Electronics Systems

Nov 24, 2020 - Learn more about how using piecewise linear circuit models rather than models with full SPICE-level accuracy to perform earlier simulation.

Synopsys Low Power Workshop Offers Breadth and Depth

Jun 18, 2019 - Learn about power management for both chip verification and implementation, the emerging importance of pre-RTL UPF checks and the scalability of UPF for large designs.

Improving EMI Performance Through Simulation

Sep 12, 2018 - Here's a method for improving EMI performance through simulation during the product design phase. This will ultimately reduce the cost of hardware verification and improve productivity.