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Power Estimation: Early Warning System Or False Alarm?

Sep 10, 2015 - Experts at the table, part 1: Is power estimation good enough to make design decisions and to provide confidence in final silicon?

Powerful New Standard

Feb 11, 2016 - A new version of IEEE 1801 enables complete power-aware flows to be constructed using a meet-in-the-middle concept. What will it mean to you and what new parts of the flow will it ...

Making Software Better

Aug 7, 2014 - After years of warnings that software developers weren't worrying about power, it’s time to step back and re-assess. Are we making progress?

The Trouble With Abstractions

Aug 27, 2015 - With all of the data needed for system tradeoffs coming from downstream, how well is design abstraction really working?

Virtual Prototyping Takes Off

Dec 3, 2014 - More cores and clusters complicate every side of the design through verification flow. What is the impact of black-box IP?

What Happened To ESL

Aug 27, 2015 - Has the ESL methodology lived up to its promises?

Who Pays for EDA Shift Left?

Feb 12, 2015 - The industry is changing and more information is flying around at an ever-faster pace. It is intended to reduce costs for semiconductor companies, but who is footing the bill?

With Responsibility Comes Power

Feb 12, 2015 - Who is responsible for ensuring a chip is within its power budget and are they being given the tools to do the job?

Synopsys’ ESL Power Analysis

Mar 18, 2014 - This article addresses the question, "what tools or methods do architects and developers have or should have to define a realistic power budget at the system level?" System-level ...

CustomExplorer Ultra: Mixed-signal Regression Management and Debug Environment

CustomExplorer Ultra is a comprehensive regression management and debug environment for mixed-signal SoC verification. Tightly integrated with Synopsys’ CustomSim simulator and CustomSim/VCS ...