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SaberRD: Ingeteam Interview by Powersys

Sep 11, 2018 - Powersys had the chance to interview Alain Sanchez, IMD-Industrial & Marine Drives, Product Technician at Ingeteam. In this interview, Alain discusses the benefits of using SaberRD ...

Faster Software Development using Hybrid Prototyping over PCIe Real World ...

Nov 13, 2019 - What if you could perform early embedded software development and HW-SW co-validation at 125MHz FPGA-based prototyping speed with the debugging flexibility of virtual prototyping?

Faster Verification Closure from IP to SoC Using the Verification Continuum ...

Dec 4, 2019 - The webinar delves into how the Synopsys end-to-end verification strategy scales from IP-level functional verification to full system-level validation & performance analysis using ...

Verifying Functional Safety Designs with Fault Simulation

Apr 14, 2020 - This webinar presents a methodology to effectively verify the functional safety logic implemented by Synplify Premier at the early stages of the design flow using fault ...

Faster Formal Verification Closure for Datapath in AI & Processor Designs

May 20, 2020 - Learn how to get closure with datapath verification using the Synopsys VC Formal DPV app along with how to make the C/C++ model ready for formal equivalence checking with the RTL ...

FPGA Prototyping: Why Build-Your-Own-Boards Aren’t Cost Effective

Jun 8, 2020 - Large semiconductor organizations have all transitioned to using high-end, scalable commercial prototyping systems for software bring-up and hardware/software validation tasks. ...

Perform Multi-Voltage Checks Faster with Low Power Signoff

Sep 16, 2020 - This webinar will highlight the benefits of tight integration between P&R and low power signoff tools.

Exascale Emulation Debug Challenges

Apr 11, 2019 - Learn how to address the 3 primary verification challenges of complex SoCs: reducing the effort to find the time window around the root cause of a test failure, reproducing the root ...

Formal Signoff

What’s good enough coverage? What makes one assertion better than another? Find out in this video as well as where the potential holes are in verification.

Joint Optimization of Hardware and Compiler: Modeling AI Accelerators Using ...

This presentation proposes a novel approach for joint optimization of algorithms/compilers and hardware architecture. The top-down/integrated approach that leverages the latest machine learning ...